From owner-svn-src-all@FreeBSD.ORG Tue May 24 05:34:45 2011 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id EC39D106566B; Tue, 24 May 2011 05:34:45 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id C33AB8FC18; Tue, 24 May 2011 05:34:45 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p4O5YjkG053520; Tue, 24 May 2011 05:34:45 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p4O5YjXM053518; Tue, 24 May 2011 05:34:45 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201105240534.p4O5YjXM053518@svn.freebsd.org> From: Adrian Chadd Date: Tue, 24 May 2011 05:34:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r222240 - head/sys/dev/ath/ath_hal/ar5416 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 May 2011 05:34:46 -0000 Author: adrian Date: Tue May 24 05:34:45 2011 New Revision: 222240 URL: http://svn.freebsd.org/changeset/base/222240 Log: Add in descriptions for TX descriptor fields ctl8-11 - these fields control the antenna control bits for the four TX series and the TPC settings for TX series 1, 2, 3. The specifics: * The TPC setting for TX series 0 is handled in ctl0. * TPC is currently disabled, so the per-packet TX power is set via the global per-rate TX power register, not per packet. * The antenna control bits don't matter for AR5416 and later so they should stay 0 (which they currently do); they may be set for Kite but as there's no TX diversity supported at the moment (it requires the NIC to be built with an external antenna switch, matching how antenna diversity is done on legacy NICs), so again keep them 0. This is in preparation for supporting per-rate TPC on the AR5416 and later. The Kite (and soon to come Kiwi) code sets ctl8-11 to 0x0, which doesn't have any effect at the moment. When TPC is enabled it would result in the second, third and fourth TX series attmpts to be done with a TX power of 0. This commit doesn't change that; it'll be followed up with some commits to properly set the TPC registers appropriately. Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416desc.h Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416desc.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416desc.h Tue May 24 02:19:45 2011 (r222239) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416desc.h Tue May 24 05:34:45 2011 (r222240) @@ -205,6 +205,29 @@ struct ar5416_desc { #define AR_STBC2 0x40000000 #define AR_STBC3 0x80000000 +/* ds_ctl8 */ +#define AR_AntCtl0 0x00ffffff +#define AR_AntCtl0_S 0 +/* Xmit 0 TPC is AR_XmitPower in ctl0 */ + +/* ds_ctl9 */ +#define AR_AntCtl1 0x00ffffff +#define AR_AntCtl1_S 0 +#define AR_XmitPower1 0xff000000 +#define AR_XmitPower1_S 24 + +/* ds_ctl10 */ +#define AR_AntCtl2 0x00ffffff +#define AR_AntCtl2_S 0 +#define AR_XmitPower2 0xff000000 +#define AR_XmitPower2_S 24 + +/* ds_ctl11 */ +#define AR_AntCtl3 0x00ffffff +#define AR_AntCtl3_S 0 +#define AR_XmitPower3 0xff000000 +#define AR_XmitPower3_S 24 + /************* * TX Status * *************/