From owner-freebsd-mips@FreeBSD.ORG Sat Oct 5 17:18:51 2013 Return-Path: Delivered-To: freebsd-mips@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 52069D39 for ; Sat, 5 Oct 2013 17:18:51 +0000 (UTC) (envelope-from adrian.chadd@gmail.com) Received: from mail-pb0-x236.google.com (mail-pb0-x236.google.com [IPv6:2607:f8b0:400e:c01::236]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 2C3A62C25 for ; Sat, 5 Oct 2013 17:18:51 +0000 (UTC) Received: by mail-pb0-f54.google.com with SMTP id ro12so5315923pbb.13 for ; Sat, 05 Oct 2013 10:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:sender:date:message-id:subject:from:to:content-type; bh=KV9PKgf3fohsZbVCb1nCjX6H2z4/ZNCF1ueqSXNyM6g=; b=wKnXp07vDrw5VAGtuV/8Aag+BbpQZlYdb1pNU114OSeqMr1FZcBg8qdahgvgwLaUmO o9u6hkN3Kd8l6ExguDCyxyWSVD22peLaLuqU1fqz35QEL1eCaGpwIHzmO9DocE4IDuH8 vBKxKcnj55hX5Z6fijgaJUc03gs97CVo6Yz1PV240RYVyUywd5ZDI+wFnped9Ez73zYr 25xl94vaiFum+tBzAZW2VVfoQsXcfOzzRrYfMEaMqeMQxoBWAyYUpalHSCsJmZMUzT59 Tfpb/1/rtxvDwiY3fTQ8ZyNxrNZhPmszbkDPOAFn3jAexH679Z9qOGno417EY2Mc+jyQ 8ahg== MIME-Version: 1.0 X-Received: by 10.68.52.170 with SMTP id u10mr21159502pbo.34.1380993530555; Sat, 05 Oct 2013 10:18:50 -0700 (PDT) Sender: adrian.chadd@gmail.com Received: by 10.70.42.10 with HTTP; Sat, 5 Oct 2013 10:18:50 -0700 (PDT) Date: Sat, 5 Oct 2013 10:18:50 -0700 X-Google-Sender-Auth: esd-vnBp3v1QkeHQLw41lGtWTUc Message-ID: Subject: How's bus-space stuff supposed to work with superscalar MIPS? From: Adrian Chadd To: "freebsd-mips@freebsd.org" Content-Type: text/plain; charset=ISO-8859-1 X-Content-Filtered-By: Mailman/MimeDel 2.1.14 X-BeenThere: freebsd-mips@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to MIPS List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 05 Oct 2013 17:18:51 -0000 Hi all, I've been bringing up the AR9344 PHY and after a lot of digging, I discovered that I can fix things by changing ARGE_WRITE() (ie, write to the ethernet space registers) to: bus_write_4(); bus_read_4(); .. to (what I'm guessing here) flush the write out before the next instruction is run. So, given this particular hilarity has shown up, what's the story with doing IO accesses on a superscalar MIPS CPU? If it's going to kseg1, is it somehow going to magically enforce ordering? Or am I right in thinking we will need explicit barriers here? I'd like to sneak this into the initial mips74k bringup support that I'm going to commit to -HEAD soon. Thanks, -adrian