From owner-freebsd-arm@FreeBSD.ORG Sat Aug 3 11:51:48 2013 Return-Path: Delivered-To: arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 52AF387B for ; Sat, 3 Aug 2013 11:51:48 +0000 (UTC) (envelope-from ray@freebsd.org) Received: from smtp.dlink.ua (smtp.dlink.ua [193.138.187.146]) by mx1.freebsd.org (Postfix) with ESMTP id 0C29B2046 for ; Sat, 3 Aug 2013 11:51:47 +0000 (UTC) Received: from rnote.ddteam.net (215-174-133-95.pool.ukrtel.net [95.133.174.215]) (Authenticated sender: ray) by smtp.dlink.ua (Postfix) with ESMTPSA id B9D10C4958; Sat, 3 Aug 2013 14:51:39 +0300 (EEST) Date: Sat, 3 Aug 2013 14:51:35 +0300 From: Aleksandr Rybalko To: Mark R V Murray Subject: Re: PATCH: get_cyclecount() on ARMv6 and better Message-Id: <20130803145135.38196156.ray@freebsd.org> In-Reply-To: <78D22A66-86E5-43B1-ABCA-7BF14F8061AB@grondar.org> References: <78D22A66-86E5-43B1-ABCA-7BF14F8061AB@grondar.org> Organization: FreeBSD.ORG X-Mailer: Sylpheed 3.1.2 (GTK+ 2.24.5; amd64-portbld-freebsd9.0) X-Operating-System: FreeBSD Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: "freebsd-arm@freebsd.org" X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Aug 2013 11:51:48 -0000 On Sat, 3 Aug 2013 10:24:40 +0100 Mark R V Murray wrote: > Hi folks > > The CSPRNG used to drive /dev/random is Yarrow, and it needs good > timing jitter to produce decent numbers. > > The i86_32 and i86_64 platforms both have the TSC register, wrapped > in the get_cyclecount() inline function, but the ARM platform doesn't > use its equivalent, the CCNT register. The alternative, using system > time, loses LOTS of low-bit jitter, and is certainly worth improving > upon. > > I'm at the early stages of testing the patch below (I only have RPi), > and would like to get some comments and reviews, please. I am very > doubtful indeed that I got the #ifdefs right - they are a bit of a > minefield! ;-) > > The patch returns the 32-bit CCNT register as the 64-bit quantity > that get_cyclecount() provides on all platforms; this is a very minor > problem, but I suppose I could figure out some kind of crude carry > mechanism and force the number to increment beyond 32 bits; I doubt > its worth it though, as its the low bits that provide the jitter. > > Thanks in advance! > > M > -- > Mark R V Murray > > Index: cpu.h > =================================================================== > --- cpu.h (revision 253832) > +++ cpu.h (working copy) > @@ -5,6 +5,9 @@ > #define MACHINE_CPU_H > > #include > +#ifndef _KERNEL > +#include > +#endif > > void cpu_halt(void); > void swi_vm(void *); > @@ -13,11 +16,26 @@ > static __inline uint64_t > get_cyclecount(void) > { > +#if defined (__ARM_ARCH_7__) || \ > + defined (__ARM_ARCH_7A__) || \ > + defined (__ARM_ARCH_6__) || \ > + defined (__ARM_ARCH_6J__) || \ > + defined (__ARM_ARCH_6K__) || \ > + defined (__ARM_ARCH_6T2__) || \ > + defined (__ARM_ARCH_6Z__) || \ > + defined (__ARM_ARCH_6ZK__) > + > + uint32_t ccnt; > + > + /* Read CCNT. Darn; its only 32 bits. */ > + __asm __volatile("mrc p15, 0, %0, c9, c13, 0": "=r" (ccnt)); > + return ((uint64_t)ccnt); > +#else > struct bintime bt; > > binuptime(&bt); > return ((uint64_t)bt.sec << 56 | bt.frac >> 8); > - > +#endif > } > #endif > > Hi Mark! Do we setup Performance Monitor Control Register before use that counter? WBW -- Aleksandr Rybalko