From owner-p4-projects@FreeBSD.ORG Mon Jan 7 07:55:03 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id B3E0616A528; Mon, 7 Jan 2008 07:55:03 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 6EFFD16A49A for ; Mon, 7 Jan 2008 07:55:03 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 5DABD13C459 for ; Mon, 7 Jan 2008 07:55:03 +0000 (UTC) (envelope-from imp@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.1/8.14.1) with ESMTP id m077t3L8033571 for ; Mon, 7 Jan 2008 07:55:03 GMT (envelope-from imp@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.1/8.14.1/Submit) id m077t3dg033564 for perforce@freebsd.org; Mon, 7 Jan 2008 07:55:03 GMT (envelope-from imp@freebsd.org) Date: Mon, 7 Jan 2008 07:55:03 GMT Message-Id: <200801070755.m077t3dg033564@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to imp@freebsd.org using -f From: Warner Losh To: Perforce Change Reviews Cc: Subject: PERFORCE change 132690 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Jan 2008 07:55:04 -0000 http://perforce.freebsd.org/chv.cgi?CH=132690 Change 132690 by imp@imp_paco-paco on 2008/01/07 07:54:29 Prefer the mips2 method for cache operations. This eliminates a few more undefines. We likely can also delete cache.S. But we should evaluate OpenBSD's cache_7k and cache_5k files to see if they are relevant or not to these operations. Affected files ... .. //depot/projects/mips2-jnpr/src/sys/conf/files.mips#6 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/db_interface.c#4 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#10 edit .. //depot/projects/mips2-jnpr/src/sys/mips/mips/pmap.c#15 edit Differences ... ==== //depot/projects/mips2-jnpr/src/sys/conf/files.mips#6 (text+ko) ==== @@ -28,7 +28,7 @@ # Phase 2 # ---------------------------------------------------------------------- -mips/mips/cache.S standard +###mips/mips/cache.S standard #xxx #mips/mips/cpuconf.c standard mips/mips/machdep.c standard @@ -67,8 +67,8 @@ mips/mips/tlb.S standard mips/mips/busdma_machdep.c standard -#mips/mips/cache.c standard -#mips/mips/cache_mipsNN.c standard +mips/mips/cache.c standard +mips/mips/cache_mipsNN.c standard #mips/mips/copystr.S standard mips/mips/db_disasm.c optional ddb mips/mips/db_interface.c optional ddb ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/db_interface.c#4 (text+ko) ==== @@ -50,6 +50,7 @@ #include #include +#include #include #include #include @@ -208,8 +209,8 @@ *dst++ = *data++; } - Mips_HitSyncSCache(addr, size); /* Flush D and S caches */ - Mips_SyncICache(addr, size); /* Invalidate I cache */ + mips_icache_sync_range((db_addr_t) addr, size); + mips_dcache_wbinv_range((db_addr_t) addr, size); } (void)kdb_jmpbuf(prev_jb); return (ret); ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/machdep.c#10 (text+ko) ==== @@ -79,6 +79,7 @@ #include #include #include +#include #include #include #include @@ -456,7 +457,10 @@ * entries needed and Invoke Cache Config routines * here, based on CPU-type. */ +#ifdef UNIMPLEMENTED + /* XXX this is done in mips_cpu_init() now, I think*/ cpucfg = Mips_ConfigCache(); +#endif num_tlbentries = 64; Mips_SetWIRED(0); Mips_TLBFlush(num_tlbentries); @@ -483,7 +487,8 @@ /* * Clear out the I and D caches. */ - Mips_SyncCache(); + mips_icache_sync_all(); + mips_dcache_wbinv_all(); /* * Mask all interrupts. Each interrupt will be enabled ==== //depot/projects/mips2-jnpr/src/sys/mips/mips/pmap.c#15 (text+ko) ==== @@ -98,6 +98,7 @@ #include #endif +#include #include #include @@ -1757,8 +1758,8 @@ */ if (!is_kernel_pmap(pmap) && (pmap == &curproc->p_vmspace->vm_pmap) && (prot & VM_PROT_EXECUTE)) { - Mips_SyncICache(va, NBPG); - Mips_HitSyncSCache(va, NBPG); + mips_icache_sync_range(va, NBPG); + mips_dcache_wbinv_range(va, NBPG); } vm_page_unlock_queues(); PMAP_UNLOCK(pmap); @@ -1883,8 +1884,8 @@ */ if (pmap == &curproc->p_vmspace->vm_pmap) { va &= ~PAGE_MASK; - Mips_SyncICache(va, NBPG); - Mips_HitSyncSCache(va, NBPG); + mips_icache_sync_range(va, NBPG); + mips_dcache_wbinv_range(va, NBPG); } }