Date: Tue, 30 Sep 2003 14:39:48 -0700 (PDT) From: Peter Wemm <peter@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 38921 for review Message-ID: <200309302139.h8ULdm0M025495@repoman.freebsd.org>
next in thread | raw e-mail | index | archive | help
http://perforce.freebsd.org/chv.cgi?CH=38921 Change 38921 by peter@peter_hammer on 2003/09/30 14:39:43 tidy some stuff up. There is no need for the startup glue code to be in asm when it can be in init_secondary(). Affected files ... .. //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#10 edit .. //depot/projects/hammer/sys/amd64/amd64/mpboot.s#7 edit Differences ... ==== //depot/projects/hammer/sys/amd64/amd64/mp_machdep.c#10 (text+ko) ==== @@ -316,16 +316,17 @@ /* XXX: List I/O APICs? They are done differently now. */ } -#ifdef SMP_ME_HARDER /* * AP cpu's call this to sync up protected mode. */ void init_secondary(void) { +#ifdef SMP_ME_HARDER int gsel_tss; int x, myid = bootAP; u_int cr0; + u_int32 value; gdt_segs[GPRIV_SEL].ssd_base = (long) &SMP_prvspace[myid]; gdt_segs[GPROC0_SEL].ssd_base = @@ -363,8 +364,17 @@ cr0 = rcr0(); cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); load_cr0(cr0); + + /* Disable local apic just to be sure. */ + value = lapic->svr; + value &= ~(APIC_SVR_SWEN); + lapic->svr = value; + + mp_naps++; + + ap_init(); /* kick things off, this does not return */ +#endif } -#endif /******************************************************************* * local functions and data ==== //depot/projects/hammer/sys/amd64/amd64/mpboot.s#7 (text+ko) ==== @@ -43,22 +43,14 @@ /* * the APs enter here from their trampoline code (bootMP, below) */ + .section .data32 .p2align 4 - .section .data32 .code32 -NON_GPROF_ENTRY(MPentry) - /* - * Enable features on this processor. We don't support SMP on - * CPUs older than a Pentium, so we know that we can use the cpuid - * instruction. - */ - movl $1,%eax - cpuid /* Retrieve features */ + .globl MPentry +MPentry: movl %cr4,%eax - orl $CR4_PSE,%eax /* Enable PSE */ - orl $CR4_PGE,%eax /* Enable PGE */ - orl $CR4_PAE, %eax + orl $CR4_PSE|CR4_PGE|CR4_PAE,%eax /* Enable features */ movl %eax,%cr4 /* Now enable paging mode */ @@ -69,45 +61,18 @@ movl %eax,%cr0 /* let the games begin! */ movl bootSTK32,%esp /* boot stack end loc. */ - pushl $mp_begin /* jump to high mem */ +#ifdef SMP_ME_HARDER /* 64 bit reference in 32 bit code */ + pushl $init_secondary /* jump to high mem */ +#endif ret - /* - * Wait for the booting CPU to signal startup - */ -mp_begin: /* now running relocated at KERNBASE */ - .code64 -#ifdef SMP_ME_HARDER - call init_secondary /* load i386 tables */ -#endif - - /* disable the APIC, just to be SURE */ - movq lapic, %rdx - movl LA_SVR(%rdx), %eax /* get spurious vector reg. */ - andl $~APIC_SVR_SWEN, %eax /* clear software enable bit */ - movl %eax, LA_SVR(%rdx) - - /* signal our startup to the BSP */ - incl mp_naps /* signal BSP */ - - /* Now, let's prepare for some REAL WORK :-) This doesn't return. */ - call ap_init - -/* - * This is the embedded trampoline or bootstrap that is - * copied into 'real-mode' low memory, it is where the - * secondary processor "wakes up". When it is executed - * the processor will eventually jump into the routine - * MPentry, which resides in normal kernel text above - * 1Meg. -jackv - */ - .p2align 4 -BOOTMP1: +BOOTMP_start: -NON_GPROF_ENTRY(bootMP) - .code16 + .code16 + .globl bootMP +bootMP: cli /* First guarantee a 'clean slate' */ xorl %eax, %eax @@ -166,9 +131,6 @@ /* this will be modified by mpInstallTramp() */ ljmp $0x08, $0 /* far jmp to MPentry() */ -dead: hlt /* We should never get here */ - jmp dead - /* * MP boot strap Global Descriptor Table */ @@ -228,11 +190,11 @@ /* * GDT pointer for the lgdt call */ - .globl mp_gdtbase MP_GDTptr: mp_gdtlimit: .word 0x0028 + .globl mp_gdtbase mp_gdtbase: /* this will be modified by mpInstallTramp() */ .long 0 @@ -246,7 +208,8 @@ IdlePTD32: .long 0 -BOOTMP2: +BOOTMP_end: + .globl bootMP_size bootMP_size: - .long BOOTMP2 - BOOTMP1 + .long BOOTMP_end - BOOTMP_start
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200309302139.h8ULdm0M025495>