Date: Tue, 11 Oct 2011 22:40:12 GMT From: Mark Tinguely <marktinguely@gmail.com> To: freebsd-arm@FreeBSD.org Subject: Re: arm/161498: [patch] ARM RAS code can fail to restart an atomic sequence. Message-ID: <201110112240.p9BMeCQ5040747@freefall.freebsd.org>
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The following reply was made to PR arm/161498; it has been noted by GNATS.
From: Mark Tinguely <marktinguely@gmail.com>
To: Ian Lepore <freebsd@damnhippie.dyndns.org>
Cc: FreeBSD-gnats-submit@FreeBSD.org
Subject: Re: arm/161498: [patch] ARM RAS code can fail to restart an atomic
sequence.
Date: Tue, 11 Oct 2011 17:13:30 -0500
On 10/11/2011 12:42 PM, Ian Lepore wrote:
> The "normal" RAS sequence goes like this:
>
> On entry, RAS_START = 0x00000000, RAS_END = 0xffffffff
>
> 1: Set RAS_START to address of Step 1
> 2: Set RAS_END to address of Step 4
> 3: Do the atomic operation
> 4: Set RAS_START to 0x00000000
> 5: Set RAS_END to 0xffffffff
good job!
I am looking forward to ARMv6/ARMv7 to replace these with
ldrex/strex/clrex calls.
Devil's advocate: a person can now put any value in RAS_START and wait
for an interrupt. I don't see that doing them any good. In the past they
could do this only if the (RAS_START < PC). In a uni-processor, we
cannot overlap these critical sections. We are assuming that critical
sections are made by an atomic command because we do not check to see if
(RAS_START < PC). Does the RAS_END comparison buy us anything? At this
point.
RAS_END == 0xffff_ffff when interrupt is between step 1 and 2
RAS_END == address of step 5
In both cases, (PC <= RAS_END)
--Mark.
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