From owner-freebsd-arm@FreeBSD.ORG Thu Jun 21 09:47:44 2012 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 054481065673; Thu, 21 Jun 2012 09:47:44 +0000 (UTC) (envelope-from mavbsd@gmail.com) Received: from mail-lb0-f182.google.com (mail-lb0-f182.google.com [209.85.217.182]) by mx1.freebsd.org (Postfix) with ESMTP id 3DC258FC0A; Thu, 21 Jun 2012 09:47:43 +0000 (UTC) Received: by lbon10 with SMTP id n10so2333785lbo.13 for ; Thu, 21 Jun 2012 02:47:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=sender:message-id:date:from:user-agent:mime-version:to:subject :content-type:content-transfer-encoding; bh=f9c5yrNr8i7YfFLbjT/wqb7ZCpPAvLe5MROec25VN+w=; b=HI2pXI8bSPf9KlpZPekPKpRTccHT7lipzz5ZI8DB4UfVeQXFFzd0V/TW72aQeHQ+P0 uKE15Yka/l2Sbv+OT+u/St1AJwDyPOLwRWcNO/FcJqfLD2uwA2Iq3ZoFfFsPrFsCR7ZE JEhTRs+BCQMcr5SJfXIsItrBpsNmGkiKRRM7s0/0sMetNtkSUUf70s4DjWSE9PZl3G1M ZKptznJZUdypYe+oThlNASmAobs+zg+DaKOokYFzj5uvWg1Dj1q1uiHqq5QjTbn+OR0J OsHDIGtnPz1YIoVRFVlIZKdCgTCq8b7mXDtM6cPdnKwFGE2ux5THi/hDDWd5jxdUB/tf nCMg== Received: by 10.112.29.131 with SMTP id k3mr11419867lbh.53.1340272061901; Thu, 21 Jun 2012 02:47:41 -0700 (PDT) Received: from mavbook2.mavhome.dp.ua (pc.mavhome.dp.ua. [212.86.226.226]) by mx.google.com with ESMTPS id k4sm18190370lbb.12.2012.06.21.02.47.39 (version=SSLv3 cipher=OTHER); Thu, 21 Jun 2012 02:47:40 -0700 (PDT) Sender: Alexander Motin Message-ID: <4FE2EDBA.1030505@FreeBSD.org> Date: Thu, 21 Jun 2012 12:47:38 +0300 From: Alexander Motin User-Agent: Mozilla/5.0 (X11; FreeBSD amd64; rv:12.0) Gecko/20120506 Thunderbird/12.0.1 MIME-Version: 1.0 To: freebsd-arm@FreeBSD.org Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: Subject: Cache write-back issue on Marvell SoC (SheevaPlug) X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Jun 2012 09:47:44 -0000 Hi. Trying to localize regular data corruption during writes (reads seems not affected) to SATA disk on SheevaPlug box I've found out that it is probably result of cache coherency issue. Reading data back shows that each time exactly 32 sequential aligned data bytes are corrupted. That, if I understand correctly, matches single cache line size/offset. I've found out that such dirty hack with flushing all D-cache after doing normal bus_dmamap_sync() fixes the situation: --- mvs.c (revision 237359) +++ mvs.c (working copy) @@ -1307,6 +1312,10 @@ mvs_dmasetprd(void *arg, bus_dma_segment_t *segs, bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map, ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ? BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE)); +#if defined(__arm__) + if (slot->ccb->ccb_h.flags & CAM_DIR_OUT) + cpu_dcache_wbinv_all(); +#endif if (ch->basic_dma) mvs_legacy_execute_transaction(slot); else Unluckily I have no idea in arm assembler and cache control interfaces. Could somebody recheck existing D-cache range write-back code, because there seems to be a problem? -- Alexander Motin