From owner-svn-src-head@freebsd.org Mon Oct 2 16:21:21 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 9F1E4E0DB6F; Mon, 2 Oct 2017 16:21:21 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 59CF76DA84; Mon, 2 Oct 2017 16:21:21 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v92GLKhs023084; Mon, 2 Oct 2017 16:21:20 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v92GLKTX023082; Mon, 2 Oct 2017 16:21:20 GMT (envelope-from manu@FreeBSD.org) Message-Id: <201710021621.v92GLKTX023082@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Mon, 2 Oct 2017 16:21:20 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r324211 - head/sys/arm/allwinner/clkng X-SVN-Group: head X-SVN-Commit-Author: manu X-SVN-Commit-Paths: head/sys/arm/allwinner/clkng X-SVN-Commit-Revision: 324211 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 02 Oct 2017 16:21:21 -0000 Author: manu Date: Mon Oct 2 16:21:20 2017 New Revision: 324211 URL: https://svnweb.freebsd.org/changeset/base/324211 Log: Allwinner A31 ccu: Use clock/reset IDs from dt-bindings Do not redefines resets and clocks ID which are already in the dt-bindings include directory. Those files are under dual licenced under GPL2/MIT so use them directly. Modified: head/sys/arm/allwinner/clkng/ccu_a31.c head/sys/arm/allwinner/clkng/ccu_a31.h Modified: head/sys/arm/allwinner/clkng/ccu_a31.c ============================================================================== --- head/sys/arm/allwinner/clkng/ccu_a31.c Mon Oct 2 16:12:06 2017 (r324210) +++ head/sys/arm/allwinner/clkng/ccu_a31.c Mon Oct 2 16:21:20 2017 (r324211) @@ -43,169 +43,204 @@ __FBSDID("$FreeBSD$"); #include #include +#include +#include + #include "ccu_a31.h" +/* Non-exported clocks */ +#define CLK_PLL_CPU 0 +#define CLK_PLL_AUDIO_BASE 1 +#define CLK_PLL_AUDIO 2 +#define CLK_PLL_AUDIO_2X 3 +#define CLK_PLL_AUDIO_4X 4 +#define CLK_PLL_AUDIO_8X 5 +#define CLK_PLL_VIDEO0 6 +#define CLK_PLL_VIDEO0_2X 7 +#define CLK_PLL_VE 8 +#define CLK_PLL_DDR 9 + +#define CLK_PLL_PERIPH_2X 11 +#define CLK_PLL_VIDEO1 12 +#define CLK_PLL_VIDEO1_2X 13 +#define CLK_PLL_GPU 14 +#define CLK_PLL_MIPI 15 +#define CLK_PLL9 16 +#define CLK_PLL10 17 + +#define CLK_AXI 19 +#define CLK_AHB1 20 +#define CLK_APB1 21 +#define CLK_APB2 22 + +#define CLK_MDFS 107 +#define CLK_SDRAM0 108 +#define CLK_SDRAM1 109 + +#define CLK_MBUS0 141 +#define CLK_MBUS1 142 + static struct aw_ccung_reset a31_ccu_resets[] = { - CCU_RESET(A31_RST_USB_PHY0, 0xcc, 0) - CCU_RESET(A31_RST_USB_PHY1, 0xcc, 1) - CCU_RESET(A31_RST_USB_PHY2, 0xcc, 2) + CCU_RESET(RST_USB_PHY0, 0xcc, 0) + CCU_RESET(RST_USB_PHY1, 0xcc, 1) + CCU_RESET(RST_USB_PHY2, 0xcc, 2) - CCU_RESET(A31_RST_AHB1_MIPI_DSI, 0x2c0, 1) - CCU_RESET(A31_RST_AHB1_SS, 0x2c0, 5) - CCU_RESET(A31_RST_AHB1_DMA, 0x2c0, 6) - CCU_RESET(A31_RST_AHB1_MMC0, 0x2c0, 8) - CCU_RESET(A31_RST_AHB1_MMC1, 0x2c0, 9) - CCU_RESET(A31_RST_AHB1_MMC2, 0x2c0, 10) - CCU_RESET(A31_RST_AHB1_MMC3, 0x2c0, 11) - CCU_RESET(A31_RST_AHB1_NAND1, 0x2c0, 12) - CCU_RESET(A31_RST_AHB1_NAND0, 0x2c0, 13) - CCU_RESET(A31_RST_AHB1_SDRAM, 0x2c0, 14) - CCU_RESET(A31_RST_AHB1_EMAC, 0x2c0, 17) - CCU_RESET(A31_RST_AHB1_TS, 0x2c0, 18) - CCU_RESET(A31_RST_AHB1_HSTIMER, 0x2c0, 19) - CCU_RESET(A31_RST_AHB1_SPI0, 0x2c0, 20) - CCU_RESET(A31_RST_AHB1_SPI1, 0x2c0, 21) - CCU_RESET(A31_RST_AHB1_SPI2, 0x2c0, 22) - CCU_RESET(A31_RST_AHB1_SPI3, 0x2c0, 23) - CCU_RESET(A31_RST_AHB1_OTG, 0x2c0, 24) - CCU_RESET(A31_RST_AHB1_EHCI0, 0x2c0, 26) - CCU_RESET(A31_RST_AHB1_EHCI1, 0x2c0, 27) - CCU_RESET(A31_RST_AHB1_OHCI0, 0x2c0, 29) - CCU_RESET(A31_RST_AHB1_OHCI1, 0x2c0, 30) - CCU_RESET(A31_RST_AHB1_OHCI2, 0x2c0, 31) + CCU_RESET(RST_AHB1_MIPI_DSI, 0x2c0, 1) + CCU_RESET(RST_AHB1_SS, 0x2c0, 5) + CCU_RESET(RST_AHB1_DMA, 0x2c0, 6) + CCU_RESET(RST_AHB1_MMC0, 0x2c0, 8) + CCU_RESET(RST_AHB1_MMC1, 0x2c0, 9) + CCU_RESET(RST_AHB1_MMC2, 0x2c0, 10) + CCU_RESET(RST_AHB1_MMC3, 0x2c0, 11) + CCU_RESET(RST_AHB1_NAND1, 0x2c0, 12) + CCU_RESET(RST_AHB1_NAND0, 0x2c0, 13) + CCU_RESET(RST_AHB1_SDRAM, 0x2c0, 14) + CCU_RESET(RST_AHB1_EMAC, 0x2c0, 17) + CCU_RESET(RST_AHB1_TS, 0x2c0, 18) + CCU_RESET(RST_AHB1_HSTIMER, 0x2c0, 19) + CCU_RESET(RST_AHB1_SPI0, 0x2c0, 20) + CCU_RESET(RST_AHB1_SPI1, 0x2c0, 21) + CCU_RESET(RST_AHB1_SPI2, 0x2c0, 22) + CCU_RESET(RST_AHB1_SPI3, 0x2c0, 23) + CCU_RESET(RST_AHB1_OTG, 0x2c0, 24) + CCU_RESET(RST_AHB1_EHCI0, 0x2c0, 26) + CCU_RESET(RST_AHB1_EHCI1, 0x2c0, 27) + CCU_RESET(RST_AHB1_OHCI0, 0x2c0, 29) + CCU_RESET(RST_AHB1_OHCI1, 0x2c0, 30) + CCU_RESET(RST_AHB1_OHCI2, 0x2c0, 31) - CCU_RESET(A31_RST_AHB1_VE, 0x2c4, 0) - CCU_RESET(A31_RST_AHB1_LCD0, 0x2c4, 4) - CCU_RESET(A31_RST_AHB1_LCD1, 0x2c4, 5) - CCU_RESET(A31_RST_AHB1_CSI, 0x2c4, 8) - CCU_RESET(A31_RST_AHB1_HDMI, 0x2c4, 11) - CCU_RESET(A31_RST_AHB1_BE0, 0x2c4, 12) - CCU_RESET(A31_RST_AHB1_BE1, 0x2c4, 13) - CCU_RESET(A31_RST_AHB1_FE0, 0x2c4, 14) - CCU_RESET(A31_RST_AHB1_FE1, 0x2c4, 15) - CCU_RESET(A31_RST_AHB1_MP, 0x2c4, 18) - CCU_RESET(A31_RST_AHB1_GPU, 0x2c4, 20) - CCU_RESET(A31_RST_AHB1_DEU0, 0x2c4, 23) - CCU_RESET(A31_RST_AHB1_DEU1, 0x2c4, 24) - CCU_RESET(A31_RST_AHB1_DRC0, 0x2c4, 25) - CCU_RESET(A31_RST_AHB1_DRC1, 0x2c4, 26) + CCU_RESET(RST_AHB1_VE, 0x2c4, 0) + CCU_RESET(RST_AHB1_LCD0, 0x2c4, 4) + CCU_RESET(RST_AHB1_LCD1, 0x2c4, 5) + CCU_RESET(RST_AHB1_CSI, 0x2c4, 8) + CCU_RESET(RST_AHB1_HDMI, 0x2c4, 11) + CCU_RESET(RST_AHB1_BE0, 0x2c4, 12) + CCU_RESET(RST_AHB1_BE1, 0x2c4, 13) + CCU_RESET(RST_AHB1_FE0, 0x2c4, 14) + CCU_RESET(RST_AHB1_FE1, 0x2c4, 15) + CCU_RESET(RST_AHB1_MP, 0x2c4, 18) + CCU_RESET(RST_AHB1_GPU, 0x2c4, 20) + CCU_RESET(RST_AHB1_DEU0, 0x2c4, 23) + CCU_RESET(RST_AHB1_DEU1, 0x2c4, 24) + CCU_RESET(RST_AHB1_DRC0, 0x2c4, 25) + CCU_RESET(RST_AHB1_DRC1, 0x2c4, 26) - CCU_RESET(A31_RST_AHB1_LVDS, 0x2c8, 0) + CCU_RESET(RST_AHB1_LVDS, 0x2c8, 0) - CCU_RESET(A31_RST_APB1_CODEC, 0x2d0, 0) - CCU_RESET(A31_RST_APB1_SPDIF, 0x2d0, 1) - CCU_RESET(A31_RST_APB1_DIGITAL_MIC, 0x2d0, 4) - CCU_RESET(A31_RST_APB1_DAUDIO0, 0x2d0, 12) - CCU_RESET(A31_RST_APB1_DAUDIO1, 0x2d0, 13) + CCU_RESET(RST_APB1_CODEC, 0x2d0, 0) + CCU_RESET(RST_APB1_SPDIF, 0x2d0, 1) + CCU_RESET(RST_APB1_DIGITAL_MIC, 0x2d0, 4) + CCU_RESET(RST_APB1_DAUDIO0, 0x2d0, 12) + CCU_RESET(RST_APB1_DAUDIO1, 0x2d0, 13) - CCU_RESET(A31_RST_APB2_I2C0, 0x2d8, 0) - CCU_RESET(A31_RST_APB2_I2C1, 0x2d8, 1) - CCU_RESET(A31_RST_APB2_I2C2, 0x2d8, 2) - CCU_RESET(A31_RST_APB2_I2C3, 0x2d8, 3) - CCU_RESET(A31_RST_APB2_UART0, 0x2d8, 16) - CCU_RESET(A31_RST_APB2_UART1, 0x2d8, 17) - CCU_RESET(A31_RST_APB2_UART2, 0x2d8, 18) - CCU_RESET(A31_RST_APB2_UART3, 0x2d8, 19) - CCU_RESET(A31_RST_APB2_UART4, 0x2d8, 20) - CCU_RESET(A31_RST_APB2_UART5, 0x2d8, 21) + CCU_RESET(RST_APB2_I2C0, 0x2d8, 0) + CCU_RESET(RST_APB2_I2C1, 0x2d8, 1) + CCU_RESET(RST_APB2_I2C2, 0x2d8, 2) + CCU_RESET(RST_APB2_I2C3, 0x2d8, 3) + CCU_RESET(RST_APB2_UART0, 0x2d8, 16) + CCU_RESET(RST_APB2_UART1, 0x2d8, 17) + CCU_RESET(RST_APB2_UART2, 0x2d8, 18) + CCU_RESET(RST_APB2_UART3, 0x2d8, 19) + CCU_RESET(RST_APB2_UART4, 0x2d8, 20) + CCU_RESET(RST_APB2_UART5, 0x2d8, 21) }; static struct aw_ccung_gate a31_ccu_gates[] = { - CCU_GATE(A31_CLK_AHB1_MIPIDSI, "ahb1-mipidsi", "ahb1", 0x60, 1) - CCU_GATE(A31_CLK_AHB1_SS, "ahb1-ss", "ahb1", 0x60, 5) - CCU_GATE(A31_CLK_AHB1_DMA, "ahb1-dma", "ahb1", 0x60, 6) - CCU_GATE(A31_CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1", 0x60, 8) - CCU_GATE(A31_CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1", 0x60, 9) - CCU_GATE(A31_CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1", 0x60, 10) - CCU_GATE(A31_CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1", 0x60, 11) - CCU_GATE(A31_CLK_AHB1_NAND1, "ahb1-nand1", "ahb1", 0x60, 12) - CCU_GATE(A31_CLK_AHB1_NAND0, "ahb1-nand0", "ahb1", 0x60, 13) - CCU_GATE(A31_CLK_AHB1_SDRAM, "ahb1-sdram", "ahb1", 0x60, 14) - CCU_GATE(A31_CLK_AHB1_EMAC, "ahb1-emac", "ahb1", 0x60, 17) - CCU_GATE(A31_CLK_AHB1_TS, "ahb1-ts", "ahb1", 0x60, 18) - CCU_GATE(A31_CLK_AHB1_HSTIMER, "ahb1-hstimer", "ahb1", 0x60, 19) - CCU_GATE(A31_CLK_AHB1_SPI0, "ahb1-spi0", "ahb1", 0x60, 20) - CCU_GATE(A31_CLK_AHB1_SPI1, "ahb1-spi1", "ahb1", 0x60, 21) - CCU_GATE(A31_CLK_AHB1_SPI2, "ahb1-spi2", "ahb1", 0x60, 22) - CCU_GATE(A31_CLK_AHB1_SPI3, "ahb1-spi3", "ahb1", 0x60, 23) - CCU_GATE(A31_CLK_AHB1_OTG, "ahb1-otg", "ahb1", 0x60, 24) - CCU_GATE(A31_CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1", 0x60, 26) - CCU_GATE(A31_CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1", 0x60, 27) - CCU_GATE(A31_CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1", 0x60, 29) - CCU_GATE(A31_CLK_AHB1_OHCI1, "ahb1-ohci1", "ahb1", 0x60, 30) - CCU_GATE(A31_CLK_AHB1_OHCI2, "ahb1-ohci2", "ahb1", 0x60, 31) - CCU_GATE(A31_CLK_AHB1_VE, "ahb1-ve", "ahb1", 0x64, 0) - CCU_GATE(A31_CLK_AHB1_LCD0, "ahb1-lcd0", "ahb1", 0x64, 4) - CCU_GATE(A31_CLK_AHB1_LCD1, "ahb1-lcd1", "ahb1", 0x64, 5) - CCU_GATE(A31_CLK_AHB1_CSI, "ahb1-csi", "ahb1", 0x64, 8) - CCU_GATE(A31_CLK_AHB1_HDMI, "ahb1-hdmi", "ahb1", 0x64, 11) - CCU_GATE(A31_CLK_AHB1_BE0, "ahb1-be0", "ahb1", 0x64, 12) - CCU_GATE(A31_CLK_AHB1_BE1, "ahb1-be1", "ahb1", 0x64, 13) - CCU_GATE(A31_CLK_AHB1_FE0, "ahb1-fe0", "ahb1", 0x64, 14) - CCU_GATE(A31_CLK_AHB1_FE1, "ahb1-fe1", "ahb1", 0x64, 15) - CCU_GATE(A31_CLK_AHB1_MP, "ahb1-mp", "ahb1", 0x64, 18) - CCU_GATE(A31_CLK_AHB1_GPU, "ahb1-gpu", "ahb1", 0x64, 20) - CCU_GATE(A31_CLK_AHB1_DEU0, "ahb1-deu0", "ahb1", 0x64, 23) - CCU_GATE(A31_CLK_AHB1_DEU1, "ahb1-deu1", "ahb1", 0x64, 24) - CCU_GATE(A31_CLK_AHB1_DRC0, "ahb1-drc0", "ahb1", 0x64, 25) - CCU_GATE(A31_CLK_AHB1_DRC1, "ahb1-drc1", "ahb1", 0x64, 26) + CCU_GATE(CLK_AHB1_MIPIDSI, "ahb1-mipidsi", "ahb1", 0x60, 1) + CCU_GATE(CLK_AHB1_SS, "ahb1-ss", "ahb1", 0x60, 5) + CCU_GATE(CLK_AHB1_DMA, "ahb1-dma", "ahb1", 0x60, 6) + CCU_GATE(CLK_AHB1_MMC0, "ahb1-mmc0", "ahb1", 0x60, 8) + CCU_GATE(CLK_AHB1_MMC1, "ahb1-mmc1", "ahb1", 0x60, 9) + CCU_GATE(CLK_AHB1_MMC2, "ahb1-mmc2", "ahb1", 0x60, 10) + CCU_GATE(CLK_AHB1_MMC3, "ahb1-mmc3", "ahb1", 0x60, 11) + CCU_GATE(CLK_AHB1_NAND1, "ahb1-nand1", "ahb1", 0x60, 12) + CCU_GATE(CLK_AHB1_NAND0, "ahb1-nand0", "ahb1", 0x60, 13) + CCU_GATE(CLK_AHB1_SDRAM, "ahb1-sdram", "ahb1", 0x60, 14) + CCU_GATE(CLK_AHB1_EMAC, "ahb1-emac", "ahb1", 0x60, 17) + CCU_GATE(CLK_AHB1_TS, "ahb1-ts", "ahb1", 0x60, 18) + CCU_GATE(CLK_AHB1_HSTIMER, "ahb1-hstimer", "ahb1", 0x60, 19) + CCU_GATE(CLK_AHB1_SPI0, "ahb1-spi0", "ahb1", 0x60, 20) + CCU_GATE(CLK_AHB1_SPI1, "ahb1-spi1", "ahb1", 0x60, 21) + CCU_GATE(CLK_AHB1_SPI2, "ahb1-spi2", "ahb1", 0x60, 22) + CCU_GATE(CLK_AHB1_SPI3, "ahb1-spi3", "ahb1", 0x60, 23) + CCU_GATE(CLK_AHB1_OTG, "ahb1-otg", "ahb1", 0x60, 24) + CCU_GATE(CLK_AHB1_EHCI0, "ahb1-ehci0", "ahb1", 0x60, 26) + CCU_GATE(CLK_AHB1_EHCI1, "ahb1-ehci1", "ahb1", 0x60, 27) + CCU_GATE(CLK_AHB1_OHCI0, "ahb1-ohci0", "ahb1", 0x60, 29) + CCU_GATE(CLK_AHB1_OHCI1, "ahb1-ohci1", "ahb1", 0x60, 30) + CCU_GATE(CLK_AHB1_OHCI2, "ahb1-ohci2", "ahb1", 0x60, 31) + CCU_GATE(CLK_AHB1_VE, "ahb1-ve", "ahb1", 0x64, 0) + CCU_GATE(CLK_AHB1_LCD0, "ahb1-lcd0", "ahb1", 0x64, 4) + CCU_GATE(CLK_AHB1_LCD1, "ahb1-lcd1", "ahb1", 0x64, 5) + CCU_GATE(CLK_AHB1_CSI, "ahb1-csi", "ahb1", 0x64, 8) + CCU_GATE(CLK_AHB1_HDMI, "ahb1-hdmi", "ahb1", 0x64, 11) + CCU_GATE(CLK_AHB1_BE0, "ahb1-be0", "ahb1", 0x64, 12) + CCU_GATE(CLK_AHB1_BE1, "ahb1-be1", "ahb1", 0x64, 13) + CCU_GATE(CLK_AHB1_FE0, "ahb1-fe0", "ahb1", 0x64, 14) + CCU_GATE(CLK_AHB1_FE1, "ahb1-fe1", "ahb1", 0x64, 15) + CCU_GATE(CLK_AHB1_MP, "ahb1-mp", "ahb1", 0x64, 18) + CCU_GATE(CLK_AHB1_GPU, "ahb1-gpu", "ahb1", 0x64, 20) + CCU_GATE(CLK_AHB1_DEU0, "ahb1-deu0", "ahb1", 0x64, 23) + CCU_GATE(CLK_AHB1_DEU1, "ahb1-deu1", "ahb1", 0x64, 24) + CCU_GATE(CLK_AHB1_DRC0, "ahb1-drc0", "ahb1", 0x64, 25) + CCU_GATE(CLK_AHB1_DRC1, "ahb1-drc1", "ahb1", 0x64, 26) - CCU_GATE(A31_CLK_APB1_CODEC, "apb1-codec", "apb1", 0x68, 0) - CCU_GATE(A31_CLK_APB1_SPDIF, "apb1-spdif", "apb1", 0x68, 1) - CCU_GATE(A31_CLK_APB1_DIGITAL_MIC, "apb1-digital-mic", "apb1", 0x68, 4) - CCU_GATE(A31_CLK_APB1_PIO, "apb1-pio", "apb1", 0x68, 5) - CCU_GATE(A31_CLK_APB1_DAUDIO0, "apb1-daudio0", "apb1", 0x68, 12) - CCU_GATE(A31_CLK_APB1_DAUDIO1, "apb1-daudio1", "apb1", 0x68, 13) + CCU_GATE(CLK_APB1_CODEC, "apb1-codec", "apb1", 0x68, 0) + CCU_GATE(CLK_APB1_SPDIF, "apb1-spdif", "apb1", 0x68, 1) + CCU_GATE(CLK_APB1_DIGITAL_MIC, "apb1-digital-mic", "apb1", 0x68, 4) + CCU_GATE(CLK_APB1_PIO, "apb1-pio", "apb1", 0x68, 5) + CCU_GATE(CLK_APB1_DAUDIO0, "apb1-daudio0", "apb1", 0x68, 12) + CCU_GATE(CLK_APB1_DAUDIO1, "apb1-daudio1", "apb1", 0x68, 13) - CCU_GATE(A31_CLK_APB2_I2C0, "apb2-i2c0", "apb2", 0x6c, 0) - CCU_GATE(A31_CLK_APB2_I2C1, "apb2-i2c1", "apb2", 0x6c, 1) - CCU_GATE(A31_CLK_APB2_I2C2, "apb2-i2c2", "apb2", 0x6c, 2) - CCU_GATE(A31_CLK_APB2_I2C3, "apb2-i2c3", "apb2", 0x6c, 3) - CCU_GATE(A31_CLK_APB2_UART0, "apb2-uart0", "apb2", 0x6c, 16) - CCU_GATE(A31_CLK_APB2_UART1, "apb2-uart1", "apb2", 0x6c, 17) - CCU_GATE(A31_CLK_APB2_UART2, "apb2-uart2", "apb2", 0x6c, 18) - CCU_GATE(A31_CLK_APB2_UART3, "apb2-uart3", "apb2", 0x6c, 19) - CCU_GATE(A31_CLK_APB2_UART4, "apb2-uart4", "apb2", 0x6c, 20) - CCU_GATE(A31_CLK_APB2_UART5, "apb2-uart5", "apb2", 0x6c, 21) + CCU_GATE(CLK_APB2_I2C0, "apb2-i2c0", "apb2", 0x6c, 0) + CCU_GATE(CLK_APB2_I2C1, "apb2-i2c1", "apb2", 0x6c, 1) + CCU_GATE(CLK_APB2_I2C2, "apb2-i2c2", "apb2", 0x6c, 2) + CCU_GATE(CLK_APB2_I2C3, "apb2-i2c3", "apb2", 0x6c, 3) + CCU_GATE(CLK_APB2_UART0, "apb2-uart0", "apb2", 0x6c, 16) + CCU_GATE(CLK_APB2_UART1, "apb2-uart1", "apb2", 0x6c, 17) + CCU_GATE(CLK_APB2_UART2, "apb2-uart2", "apb2", 0x6c, 18) + CCU_GATE(CLK_APB2_UART3, "apb2-uart3", "apb2", 0x6c, 19) + CCU_GATE(CLK_APB2_UART4, "apb2-uart4", "apb2", 0x6c, 20) + CCU_GATE(CLK_APB2_UART5, "apb2-uart5", "apb2", 0x6c, 21) - CCU_GATE(A31_CLK_DAUDIO0, "daudio0", "daudio0mux", 0xb0, 31) - CCU_GATE(A31_CLK_DAUDIO1, "daudio1", "daudio1mux", 0xb4, 31) + CCU_GATE(CLK_DAUDIO0, "daudio0", "daudio0mux", 0xb0, 31) + CCU_GATE(CLK_DAUDIO1, "daudio1", "daudio1mux", 0xb4, 31) - CCU_GATE(A31_CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) - CCU_GATE(A31_CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) - CCU_GATE(A31_CLK_USB_PHY2, "usb-phy2", "osc24M", 0xcc, 10) - CCU_GATE(A31_CLK_USB_OHCI0, "usb-ohci0", "osc24M", 0xcc, 16) - CCU_GATE(A31_CLK_USB_OHCI1, "usb-ohci1", "osc24M", 0xcc, 17) - CCU_GATE(A31_CLK_USB_OHCI2, "usb-ohci2", "osc24M", 0xcc, 18) + CCU_GATE(CLK_USB_PHY0, "usb-phy0", "osc24M", 0xcc, 8) + CCU_GATE(CLK_USB_PHY1, "usb-phy1", "osc24M", 0xcc, 9) + CCU_GATE(CLK_USB_PHY2, "usb-phy2", "osc24M", 0xcc, 10) + CCU_GATE(CLK_USB_OHCI0, "usb-ohci0", "osc24M", 0xcc, 16) + CCU_GATE(CLK_USB_OHCI1, "usb-ohci1", "osc24M", 0xcc, 17) + CCU_GATE(CLK_USB_OHCI2, "usb-ohci2", "osc24M", 0xcc, 18) - CCU_GATE(A31_CLK_DRAM_VE, "dram-ve", "mdfs", 0x100, 0) - CCU_GATE(A31_CLK_DRAM_CSI_ISP, "dram-csi_isp", "mdfs", 0x100, 1) - CCU_GATE(A31_CLK_DRAM_TS, "dram-ts", "mdfs", 0x100, 3) - CCU_GATE(A31_CLK_DRAM_DRC0, "dram-drc0", "mdfs", 0x100, 16) - CCU_GATE(A31_CLK_DRAM_DRC1, "dram-drc1", "mdfs", 0x100, 17) - CCU_GATE(A31_CLK_DRAM_DEU0, "dram-deu0", "mdfs", 0x100, 18) - CCU_GATE(A31_CLK_DRAM_DEU1, "dram-deu1", "mdfs", 0x100, 19) - CCU_GATE(A31_CLK_DRAM_FE0, "dram-fe0", "mdfs", 0x100, 24) - CCU_GATE(A31_CLK_DRAM_FE1, "dram-fe1", "mdfs", 0x100, 25) - CCU_GATE(A31_CLK_DRAM_BE0, "dram-be0", "mdfs", 0x100, 26) - CCU_GATE(A31_CLK_DRAM_BE1, "dram-be1", "mdfs", 0x100, 27) - CCU_GATE(A31_CLK_DRAM_MP, "dram-mp", "mdfs", 0x100, 28) + CCU_GATE(CLK_DRAM_VE, "dram-ve", "mdfs", 0x100, 0) + CCU_GATE(CLK_DRAM_CSI_ISP, "dram-csi_isp", "mdfs", 0x100, 1) + CCU_GATE(CLK_DRAM_TS, "dram-ts", "mdfs", 0x100, 3) + CCU_GATE(CLK_DRAM_DRC0, "dram-drc0", "mdfs", 0x100, 16) + CCU_GATE(CLK_DRAM_DRC1, "dram-drc1", "mdfs", 0x100, 17) + CCU_GATE(CLK_DRAM_DEU0, "dram-deu0", "mdfs", 0x100, 18) + CCU_GATE(CLK_DRAM_DEU1, "dram-deu1", "mdfs", 0x100, 19) + CCU_GATE(CLK_DRAM_FE0, "dram-fe0", "mdfs", 0x100, 24) + CCU_GATE(CLK_DRAM_FE1, "dram-fe1", "mdfs", 0x100, 25) + CCU_GATE(CLK_DRAM_BE0, "dram-be0", "mdfs", 0x100, 26) + CCU_GATE(CLK_DRAM_BE1, "dram-be1", "mdfs", 0x100, 27) + CCU_GATE(CLK_DRAM_MP, "dram-mp", "mdfs", 0x100, 28) - CCU_GATE(A31_CLK_CODEC, "codec", "pll_audio", 0x140, 31) + CCU_GATE(CLK_CODEC, "codec", "pll_audio", 0x140, 31) - CCU_GATE(A31_CLK_AVS, "avs", "pll_audio", 0x144, 31) + CCU_GATE(CLK_AVS, "avs", "pll_audio", 0x144, 31) - CCU_GATE(A31_CLK_DIGITAL_MIC, "digital-mic", "pll_audio", 0x148, 31) + CCU_GATE(CLK_DIGITAL_MIC, "digital-mic", "pll_audio", 0x148, 31) - CCU_GATE(A31_CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x150, 30) + CCU_GATE(CLK_HDMI_DDC, "hdmi-ddc", "osc24M", 0x150, 30) - CCU_GATE(A31_CLK_PS, "ps", "lcd1_ch1", 0x154, 31) + CCU_GATE(CLK_PS, "ps", "lcd1_ch1", 0x154, 31) }; static const char *pll_parents[] = {"osc24M"}; NKMP_CLK(pll_cpu_clk, - A31_CLK_PLL_CPU, /* id */ + CLK_PLL_CPU, /* id */ "pll_cpu", pll_parents, /* name, parents */ 0x00, /* offset */ 8, 5, 0, 0, /* n factor */ @@ -217,7 +252,7 @@ NKMP_CLK(pll_cpu_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK | AW_CLK_SCALE_CHANGE); /* flags */ NKMP_CLK(pll_audio_clk, - A31_CLK_PLL_AUDIO, /* id */ + CLK_PLL_AUDIO, /* id */ "pll_audio", pll_parents, /* name, parents */ 0x08, /* offset */ 8, 7, 0, 0, /* n factor */ @@ -230,7 +265,7 @@ NKMP_CLK(pll_audio_clk, static const char *pll_audio_mult_parents[] = {"pll_audio"}; FIXED_CLK(pll_audio_2x_clk, - A31_CLK_PLL_AUDIO_2X, /* id */ + CLK_PLL_AUDIO_2X, /* id */ "pll_audio-2x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ @@ -238,7 +273,7 @@ FIXED_CLK(pll_audio_2x_clk, 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_4x_clk, - A31_CLK_PLL_AUDIO_4X, /* id */ + CLK_PLL_AUDIO_4X, /* id */ "pll_audio-4x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ @@ -246,7 +281,7 @@ FIXED_CLK(pll_audio_4x_clk, 1, /* div */ 0); /* flags */ FIXED_CLK(pll_audio_8x_clk, - A31_CLK_PLL_AUDIO_8X, /* id */ + CLK_PLL_AUDIO_8X, /* id */ "pll_audio-8x", /* name */ pll_audio_mult_parents, /* parent */ 0, /* freq */ @@ -255,7 +290,7 @@ FIXED_CLK(pll_audio_8x_clk, 0); /* flags */ NM_CLK_WITH_FRAC(pll_video0_clk, - A31_CLK_PLL_VIDEO0, /* id */ + CLK_PLL_VIDEO0, /* id */ "pll_video0", pll_parents, /* name, parents */ 0x10, /* offset */ 8, 7, 0, 0, /* n factor */ @@ -267,7 +302,7 @@ NM_CLK_WITH_FRAC(pll_video0_clk, static const char *pll_video0_2x_parents[] = {"pll_video0"}; FIXED_CLK(pll_video0_2x_clk, - A31_CLK_PLL_VIDEO0_2X, /* id */ + CLK_PLL_VIDEO0_2X, /* id */ "pll_video0-2x", /* name */ pll_video0_2x_parents, /* parent */ 0, /* freq */ @@ -276,7 +311,7 @@ FIXED_CLK(pll_video0_2x_clk, 0); /* flags */ NM_CLK_WITH_FRAC(pll_ve_clk, - A31_CLK_PLL_VE, /* id */ + CLK_PLL_VE, /* id */ "pll_ve", pll_parents, /* name, parents */ 0x18, /* offset */ 8, 7, 0, 0, /* n factor */ @@ -287,7 +322,7 @@ NM_CLK_WITH_FRAC(pll_ve_clk, 24, 25); /* mode sel, freq sel */ NKMP_CLK_WITH_UPDATE(pll_ddr_clk, - A31_CLK_PLL_DDR, /* id */ + CLK_PLL_DDR, /* id */ "pll_ddr", pll_parents, /* name, parents */ 0x20, /* offset */ 8, 5, 0, 0, /* n factor */ @@ -300,7 +335,7 @@ NKMP_CLK_WITH_UPDATE(pll_ddr_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ NKMP_CLK(pll_periph_clk, - A31_CLK_PLL_PERIPH, /* id */ + CLK_PLL_PERIPH, /* id */ "pll_periph", pll_parents, /* name, parents */ 0x28, /* offset */ 8, 4, 0, 0, /* n factor */ @@ -313,7 +348,7 @@ NKMP_CLK(pll_periph_clk, static const char *pll_periph_2x_parents[] = {"pll_periph"}; FIXED_CLK(pll_periph_2x_clk, - A31_CLK_PLL_PERIPH_2X, /* id */ + CLK_PLL_PERIPH_2X, /* id */ "pll_periph-2x", /* name */ pll_periph_2x_parents, /* parent */ 0, /* freq */ @@ -322,7 +357,7 @@ FIXED_CLK(pll_periph_2x_clk, 0); /* flags */ NM_CLK_WITH_FRAC(pll_video1_clk, - A31_CLK_PLL_VIDEO1, /* id */ + CLK_PLL_VIDEO1, /* id */ "pll_video1", pll_parents, /* name, parents */ 0x30, /* offset */ 8, 7, 0, 0, /* n factor */ @@ -334,7 +369,7 @@ NM_CLK_WITH_FRAC(pll_video1_clk, static const char *pll_video1_2x_parents[] = {"pll_video1"}; FIXED_CLK(pll_video1_2x_clk, - A31_CLK_PLL_VIDEO1_2X, /* id */ + CLK_PLL_VIDEO1_2X, /* id */ "pll_video1-2x", /* name */ pll_video1_2x_parents, /* parent */ 0, /* freq */ @@ -343,7 +378,7 @@ FIXED_CLK(pll_video1_2x_clk, 0); /* flags */ NM_CLK_WITH_FRAC(pll_gpu_clk, - A31_CLK_PLL_GPU, /* id */ + CLK_PLL_GPU, /* id */ "pll_gpu", pll_parents, /* name, parents */ 0x38, /* offset */ 8, 7, 0, 0, /* n factor */ @@ -355,7 +390,7 @@ NM_CLK_WITH_FRAC(pll_gpu_clk, static const char *pll_mipi_parents[] = {"pll_video0", "pll_video1"}; NKMP_CLK(pll_mipi_clk, - A31_CLK_PLL_MIPI, /* id */ + CLK_PLL_MIPI, /* id */ "pll_mipi", pll_mipi_parents, /* name, parents */ 0x40, /* offset */ 8, 4, 0, 0, /* n factor */ @@ -367,7 +402,7 @@ NKMP_CLK(pll_mipi_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_LOCK); /* flags */ NM_CLK_WITH_FRAC(pll9_clk, - A31_CLK_PLL9, /* id */ + CLK_PLL9, /* id */ "pll9", pll_parents, /* name, parents */ 0x44, /* offset */ 8, 7, 0, 0, /* n factor */ @@ -378,7 +413,7 @@ NM_CLK_WITH_FRAC(pll9_clk, 24, 25); /* mode sel, freq sel */ NM_CLK_WITH_FRAC(pll10_clk, - A31_CLK_PLL10, /* id */ + CLK_PLL10, /* id */ "pll10", pll_parents, /* name, parents */ 0x48, /* offset */ 8, 7, 0, 0, /* n factor */ @@ -401,7 +436,7 @@ static struct clk_div_table axi_div_table[] = { }; static const char *axi_parents[] = {"cpu"}; DIV_CLK(axi_clk, - A31_CLK_AXI, /* id */ + CLK_AXI, /* id */ "axi", axi_parents, /* name, parents */ 0x50, /* offset */ 0, 2, /* shift, mask */ @@ -409,13 +444,13 @@ DIV_CLK(axi_clk, static const char *cpu_parents[] = {"osc32k", "osc24M", "pll_cpu", "pll_cpu"}; MUX_CLK(cpu_clk, - A31_CLK_CPU, /* id */ + CLK_CPU, /* id */ "cpu", cpu_parents, /* name, parents */ 0x50, 16, 2); /* offset, shift, width */ static const char *ahb1_parents[] = {"osc32k", "osc24M", "axi", "pll_periph"}; PREDIV_CLK(ahb1_clk, - A31_CLK_AHB1, /* id */ + CLK_AHB1, /* id */ "ahb1", ahb1_parents, /* name, parents */ 0x54, /* offset */ 12, 2, /* mux */ @@ -432,7 +467,7 @@ static struct clk_div_table apb1_div_table[] = { { }, }; DIV_CLK(apb1_clk, - A31_CLK_APB1, /* id */ + CLK_APB1, /* id */ "apb1", apb1_parents, /* name, parents */ 0x54, /* offset */ 8, 2, /* shift, mask */ @@ -441,7 +476,7 @@ DIV_CLK(apb1_clk, static const char *apb2_parents[] = {"osc32k", "osc24M", "pll_periph", "pll_periph"}; NM_CLK(apb2_clk, - A31_CLK_APB2, /* id */ + CLK_APB2, /* id */ "apb2", apb2_parents, /* name, parents */ 0x58, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ @@ -452,7 +487,7 @@ NM_CLK(apb2_clk, static const char *mod_parents[] = {"osc24M", "pll_periph"}; NM_CLK(nand0_clk, - A31_CLK_NAND0, "nand0", mod_parents, /* id, name, parents */ + CLK_NAND0, "nand0", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 3, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -461,7 +496,7 @@ NM_CLK(nand0_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(nand1_clk, - A31_CLK_NAND1, "nand1", mod_parents, /* id, name, parents */ + CLK_NAND1, "nand1", mod_parents, /* id, name, parents */ 0x80, /* offset */ 16, 3, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -470,7 +505,7 @@ NM_CLK(nand1_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(mmc0_clk, - A31_CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ + CLK_MMC0, "mmc0", mod_parents, /* id, name, parents */ 0x88, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -480,7 +515,7 @@ NM_CLK(mmc0_clk, AW_CLK_REPARENT); /* flags */ NM_CLK(mmc1_clk, - A31_CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ + CLK_MMC1, "mmc1", mod_parents, /* id, name, parents */ 0x8c, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -490,7 +525,7 @@ NM_CLK(mmc1_clk, AW_CLK_REPARENT); /* flags */ NM_CLK(mmc2_clk, - A31_CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ + CLK_MMC2, "mmc2", mod_parents, /* id, name, parents */ 0x90, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -500,7 +535,7 @@ NM_CLK(mmc2_clk, AW_CLK_REPARENT); /* flags */ NM_CLK(mmc3_clk, - A31_CLK_MMC2, "mmc3", mod_parents, /* id, name, parents */ + CLK_MMC2, "mmc3", mod_parents, /* id, name, parents */ 0x94, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -511,7 +546,7 @@ NM_CLK(mmc3_clk, static const char *ts_parents[] = {"osc24M", "pll_periph"}; NM_CLK(ts_clk, - A31_CLK_TS, "ts", ts_parents, /* id, name, parents */ + CLK_TS, "ts", ts_parents, /* id, name, parents */ 0x98, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -520,7 +555,7 @@ NM_CLK(ts_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(ss_clk, - A31_CLK_SS, "ss", mod_parents, /* id, name, parents */ + CLK_SS, "ss", mod_parents, /* id, name, parents */ 0x9C, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -529,7 +564,7 @@ NM_CLK(ss_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi0_clk, - A31_CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ + CLK_SPI0, "spi0", mod_parents, /* id, name, parents */ 0xA0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -538,7 +573,7 @@ NM_CLK(spi0_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi1_clk, - A31_CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ + CLK_SPI1, "spi1", mod_parents, /* id, name, parents */ 0xA4, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -547,7 +582,7 @@ NM_CLK(spi1_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi2_clk, - A31_CLK_SPI2, "spi2", mod_parents, /* id, name, parents */ + CLK_SPI2, "spi2", mod_parents, /* id, name, parents */ 0xA8, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -556,7 +591,7 @@ NM_CLK(spi2_clk, AW_CLK_HAS_GATE | AW_CLK_HAS_MUX); /* flags */ NM_CLK(spi3_clk, - A31_CLK_SPI3, "spi3", mod_parents, /* id, name, parents */ + CLK_SPI3, "spi3", mod_parents, /* id, name, parents */ 0xAC, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -577,7 +612,7 @@ MUX_CLK(daudio1mux_clk, static const char *mdfs_parents[] = {"pll_ddr", "pll_periph"}; NM_CLK(mdfs_clk, - A31_CLK_MDFS, "mdfs", mdfs_parents, /* id, name, parents */ + CLK_MDFS, "mdfs", mdfs_parents, /* id, name, parents */ 0xF0, /* offset */ 16, 2, 0, AW_CLK_FACTOR_POWER_OF_TWO, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -587,7 +622,7 @@ NM_CLK(mdfs_clk, static const char *dram_parents[] = {"pll_ddr", "pll_periph"}; NM_CLK(sdram0_clk, - A31_CLK_SDRAM0, "sdram0", dram_parents, /* id, name, parents */ + CLK_SDRAM0, "sdram0", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -595,7 +630,7 @@ NM_CLK(sdram0_clk, 0, /* gate */ AW_CLK_HAS_MUX); /* flags */ NM_CLK(sdram1_clk, - A31_CLK_SDRAM1, "sdram1", dram_parents, /* id, name, parents */ + CLK_SDRAM1, "sdram1", dram_parents, /* id, name, parents */ 0xF4, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 8, 4, 0, 0, /* m factor */ @@ -605,7 +640,7 @@ NM_CLK(sdram1_clk, static const char *befe_parents[] = {"pll_video0", "pll_video1", "pll_periph-2x", "pll_gpu", "pll9", "pll10"}; NM_CLK(be0_clk, - A31_CLK_BE0, "be0", befe_parents, /* id, name, parents */ + CLK_BE0, "be0", befe_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -614,7 +649,7 @@ NM_CLK(be0_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(be1_clk, - A31_CLK_BE1, "be1", befe_parents, /* id, name, parents */ + CLK_BE1, "be1", befe_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -623,7 +658,7 @@ NM_CLK(be1_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(fe0_clk, - A31_CLK_FE0, "fe0", befe_parents, /* id, name, parents */ + CLK_FE0, "fe0", befe_parents, /* id, name, parents */ 0x104, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -631,7 +666,7 @@ NM_CLK(fe0_clk, 31, /* gate */ AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(fe1_clk, - A31_CLK_FE1, "fe1", befe_parents, /* id, name, parents */ + CLK_FE1, "fe1", befe_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -641,7 +676,7 @@ NM_CLK(fe1_clk, static const char *mp_parents[] = {"pll_video0", "pll_video1", "pll9", "pll10"}; NM_CLK(mp_clk, - A31_CLK_MP, "mp", mp_parents, /* id, name, parents */ + CLK_MP, "mp", mp_parents, /* id, name, parents */ 0x108, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -651,7 +686,7 @@ NM_CLK(mp_clk, static const char *lcd_ch0_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x", "pll_mipi"}; NM_CLK(lcd0_ch0_clk, - A31_CLK_LCD0_CH0, "lcd0_ch0", lcd_ch0_parents, /* id, name, parents */ + CLK_LCD0_CH0, "lcd0_ch0", lcd_ch0_parents, /* id, name, parents */ 0x118, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake )*/ @@ -660,7 +695,7 @@ NM_CLK(lcd0_ch0_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(lcd1_ch0_clk, - A31_CLK_LCD1_CH0, "lcd1_ch0", lcd_ch0_parents, /* id, name, parents */ + CLK_LCD1_CH0, "lcd1_ch0", lcd_ch0_parents, /* id, name, parents */ 0x11C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake )*/ @@ -670,7 +705,7 @@ NM_CLK(lcd1_ch0_clk, static const char *lcd_ch1_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x"}; NM_CLK(lcd0_ch1_clk, - A31_CLK_LCD0_CH1, "lcd0_ch1", lcd_ch1_parents, /* id, name, parents */ + CLK_LCD0_CH1, "lcd0_ch1", lcd_ch1_parents, /* id, name, parents */ 0x12C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -679,7 +714,7 @@ NM_CLK(lcd0_ch1_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(lcd1_ch1_clk, - A31_CLK_LCD1_CH1, "lcd1_ch1", lcd_ch1_parents, /* id, name, parents */ + CLK_LCD1_CH1, "lcd1_ch1", lcd_ch1_parents, /* id, name, parents */ 0x130, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -692,7 +727,7 @@ NM_CLK(lcd1_ch1_clk, static const char *ve_parents[] = {"pll_ve"}; NM_CLK(ve_clk, - A31_CLK_VE, "ve", ve_parents, /* id, name, parents */ + CLK_VE, "ve", ve_parents, /* id, name, parents */ 0x13C, /* offset */ 16, 3, 0, 0, /* n factor */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* m factor (fake) */ @@ -701,7 +736,7 @@ NM_CLK(ve_clk, AW_CLK_HAS_GATE); /* flags */ NM_CLK(hdmi_clk, - A31_CLK_HDMI, "hdmi", lcd_ch1_parents, /* id, name, parents */ + CLK_HDMI, "hdmi", lcd_ch1_parents, /* id, name, parents */ 0x150, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -711,7 +746,7 @@ NM_CLK(hdmi_clk, static const char *mbus_parents[] = {"osc24M", "pll_periph", "pll_ddr"}; NM_CLK(mbus0_clk, - A31_CLK_MBUS0, "mbus0", mbus_parents, /* id, name, parents */ + CLK_MBUS0, "mbus0", mbus_parents, /* id, name, parents */ 0x15C, /* offset */ 16, 2, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -720,7 +755,7 @@ NM_CLK(mbus0_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mbus1_clk, - A31_CLK_MBUS1, "mbus1", mbus_parents, /* id, name, parents */ + CLK_MBUS1, "mbus1", mbus_parents, /* id, name, parents */ 0x160, /* offset */ 16, 2, 0, 0, /* n factor */ 0, 4, 0, 0, /* m factor */ @@ -730,7 +765,7 @@ NM_CLK(mbus1_clk, static const char *mipi_parents[] = {"pll_video0", "pll_video1", "pll_video0-2x", "pll_video1-2x"}; NM_CLK(mipi_dsi_clk, - A31_CLK_MIPI_DSI, "mipi_dsi", mipi_parents, /* id, name, parents */ + CLK_MIPI_DSI, "mipi_dsi", mipi_parents, /* id, name, parents */ 0x168, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 16, 4, 0, 0, /* m factor */ @@ -739,7 +774,7 @@ NM_CLK(mipi_dsi_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mipi_dsi_dphy_clk, - A31_CLK_MIPI_DSI_DPHY, "mipi_dsi_dphy", mipi_parents, /* id, name, parents */ + CLK_MIPI_DSI_DPHY, "mipi_dsi_dphy", mipi_parents, /* id, name, parents */ 0x168, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -748,7 +783,7 @@ NM_CLK(mipi_dsi_dphy_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(mipi_csi_dphy_clk, - A31_CLK_MIPI_CSI_DPHY, "mipi_csi_dphy", mipi_parents, /* id, name, parents */ + CLK_MIPI_CSI_DPHY, "mipi_csi_dphy", mipi_parents, /* id, name, parents */ 0x16C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -759,7 +794,7 @@ NM_CLK(mipi_csi_dphy_clk, static const char *iep_parents[] = {"pll_video0", "pll_video1", "pll_periph-2x", "pll_gpu", "pll9", "pll10"}; NM_CLK(iep_drc0_clk, - A31_CLK_IEP_DRC0, "iep_drc0", iep_parents, /* id, name, parents */ + CLK_IEP_DRC0, "iep_drc0", iep_parents, /* id, name, parents */ 0x180, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -768,7 +803,7 @@ NM_CLK(iep_drc0_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_drc1_clk, - A31_CLK_IEP_DRC1, "iep_drc1", iep_parents, /* id, name, parents */ + CLK_IEP_DRC1, "iep_drc1", iep_parents, /* id, name, parents */ 0x184, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -777,7 +812,7 @@ NM_CLK(iep_drc1_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_deu0_clk, - A31_CLK_IEP_DEU0, "iep_deu0", iep_parents, /* id, name, parents */ + CLK_IEP_DEU0, "iep_deu0", iep_parents, /* id, name, parents */ 0x188, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -786,7 +821,7 @@ NM_CLK(iep_deu0_clk, AW_CLK_HAS_MUX | AW_CLK_HAS_GATE); /* flags */ NM_CLK(iep_deu1_clk, - A31_CLK_IEP_DEU1, "iep_deu1", iep_parents, /* id, name, parents */ + CLK_IEP_DEU1, "iep_deu1", iep_parents, /* id, name, parents */ 0x18C, /* offset */ 0, 0, 1, AW_CLK_FACTOR_FIXED, /* n factor (fake) */ 0, 4, 0, 0, /* m factor */ @@ -796,7 +831,7 @@ NM_CLK(iep_deu1_clk, static const char *gpu_parents[] = {"pll_gpu", "pll_periph-2x", "pll_video0", "pll_video1", "pll9", "pll10"}; PREDIV_CLK(gpu_core_clk, - A31_CLK_GPU_CORE, /* id */ + CLK_GPU_CORE, /* id */ "gpu_core", gpu_parents, /* name, parents */ 0x1A0, /* offset */ 24, 3, /* mux */ @@ -805,7 +840,7 @@ PREDIV_CLK(gpu_core_clk, 24, 2, 1); /* prediv condition */ PREDIV_CLK(gpu_memory_clk, - A31_CLK_GPU_MEMORY, /* id */ + CLK_GPU_MEMORY, /* id */ "gpu_memory", gpu_parents, /* name, parents */ 0x1A4, /* offset */ 24, 3, /* mux */ @@ -814,7 +849,7 @@ PREDIV_CLK(gpu_memory_clk, 24, 2, 1); /* prediv condition */ PREDIV_CLK(gpu_hyd_clk, - A31_CLK_GPU_HYD, /* id */ + CLK_GPU_HYD, /* id */ "gpu_hyd", gpu_parents, /* name, parents */ 0x1A8, /* offset */ 24, 3, /* mux */ Modified: head/sys/arm/allwinner/clkng/ccu_a31.h ============================================================================== --- head/sys/arm/allwinner/clkng/ccu_a31.h Mon Oct 2 16:12:06 2017 (r324210) +++ head/sys/arm/allwinner/clkng/ccu_a31.h Mon Oct 2 16:21:20 2017 (r324211) @@ -29,222 +29,6 @@ #ifndef __CCU_A31_H__ #define __CCU_A31_H__ -#define A31_RST_USB_PHY0 0 -#define A31_RST_USB_PHY1 1 -#define A31_RST_USB_PHY2 2 -#define A31_RST_AHB1_MIPI_DSI 3 -#define A31_RST_AHB1_SS 4 -#define A31_RST_AHB1_DMA 5 -#define A31_RST_AHB1_MMC0 6 -#define A31_RST_AHB1_MMC1 7 -#define A31_RST_AHB1_MMC2 8 -#define A31_RST_AHB1_MMC3 9 -#define A31_RST_AHB1_NAND1 10 -#define A31_RST_AHB1_NAND0 11 -#define A31_RST_AHB1_SDRAM 12 -#define A31_RST_AHB1_EMAC 13 -#define A31_RST_AHB1_TS 14 -#define A31_RST_AHB1_HSTIMER 15 -#define A31_RST_AHB1_SPI0 16 -#define A31_RST_AHB1_SPI1 17 -#define A31_RST_AHB1_SPI2 18 -#define A31_RST_AHB1_SPI3 19 -#define A31_RST_AHB1_OTG 20 -#define A31_RST_AHB1_EHCI0 21 -#define A31_RST_AHB1_EHCI1 22 -#define A31_RST_AHB1_OHCI0 23 -#define A31_RST_AHB1_OHCI1 24 -#define A31_RST_AHB1_OHCI2 25 -#define A31_RST_AHB1_VE 26 -#define A31_RST_AHB1_LCD0 27 -#define A31_RST_AHB1_LCD1 28 -#define A31_RST_AHB1_CSI 29 -#define A31_RST_AHB1_HDMI 30 -#define A31_RST_AHB1_BE0 31 -#define A31_RST_AHB1_BE1 32 -#define A31_RST_AHB1_FE0 33 -#define A31_RST_AHB1_FE1 34 -#define A31_RST_AHB1_MP 35 -#define A31_RST_AHB1_GPU 36 -#define A31_RST_AHB1_DEU0 37 -#define A31_RST_AHB1_DEU1 38 -#define A31_RST_AHB1_DRC0 39 -#define A31_RST_AHB1_DRC1 40 -#define A31_RST_AHB1_LVDS 41 -#define A31_RST_APB1_CODEC 42 -#define A31_RST_APB1_SPDIF 43 -#define A31_RST_APB1_DIGITAL_MIC 44 -#define A31_RST_APB1_DAUDIO0 45 -#define A31_RST_APB1_DAUDIO1 46 -#define A31_RST_APB2_I2C0 47 -#define A31_RST_APB2_I2C1 48 -#define A31_RST_APB2_I2C2 49 -#define A31_RST_APB2_I2C3 50 -#define A31_RST_APB2_UART0 51 -#define A31_RST_APB2_UART1 52 -#define A31_RST_APB2_UART2 53 -#define A31_RST_APB2_UART3 54 -#define A31_RST_APB2_UART4 55 -#define A31_RST_APB2_UART5 56 - -#define A31_CLK_PLL_CPU 0 -#define A31_CLK_PLL_AUDIO_BASE 1 -#define A31_CLK_PLL_AUDIO 2 -#define A31_CLK_PLL_AUDIO_2X 3 -#define A31_CLK_PLL_AUDIO_4X 4 -#define A31_CLK_PLL_AUDIO_8X 5 -#define A31_CLK_PLL_VIDEO0 6 -#define A31_CLK_PLL_VIDEO0_2X 7 -#define A31_CLK_PLL_VE 8 -#define A31_CLK_PLL_DDR 9 -#define A31_CLK_PLL_PERIPH 10 -#define A31_CLK_PLL_PERIPH_2X 11 -#define A31_CLK_PLL_VIDEO1 12 -#define A31_CLK_PLL_VIDEO1_2X 13 -#define A31_CLK_PLL_GPU 14 -#define A31_CLK_PLL_MIPI 15 -#define A31_CLK_PLL9 16 -#define A31_CLK_PLL10 17 -#define A31_CLK_CPU 18 -#define A31_CLK_AXI 19 -#define A31_CLK_AHB1 20 -#define A31_CLK_APB1 21 -#define A31_CLK_APB2 22 -#define A31_CLK_AHB1_MIPIDSI 23 -#define A31_CLK_AHB1_SS 24 -#define A31_CLK_AHB1_DMA 25 -#define A31_CLK_AHB1_MMC0 26 -#define A31_CLK_AHB1_MMC1 27 -#define A31_CLK_AHB1_MMC2 28 -#define A31_CLK_AHB1_MMC3 29 -#define A31_CLK_AHB1_NAND1 30 -#define A31_CLK_AHB1_NAND0 31 -#define A31_CLK_AHB1_SDRAM 32 -#define A31_CLK_AHB1_EMAC 33 -#define A31_CLK_AHB1_TS 34 -#define A31_CLK_AHB1_HSTIMER 35 -#define A31_CLK_AHB1_SPI0 36 -#define A31_CLK_AHB1_SPI1 37 -#define A31_CLK_AHB1_SPI2 38 -#define A31_CLK_AHB1_SPI3 39 -#define A31_CLK_AHB1_OTG 40 -#define A31_CLK_AHB1_EHCI0 41 -#define A31_CLK_AHB1_EHCI1 42 -#define A31_CLK_AHB1_OHCI0 43 -#define A31_CLK_AHB1_OHCI1 44 -#define A31_CLK_AHB1_OHCI2 45 -#define A31_CLK_AHB1_VE 46 -#define A31_CLK_AHB1_LCD0 47 -#define A31_CLK_AHB1_LCD1 48 -#define A31_CLK_AHB1_CSI 49 -#define A31_CLK_AHB1_HDMI 50 -#define A31_CLK_AHB1_BE0 51 -#define A31_CLK_AHB1_BE1 52 -#define A31_CLK_AHB1_FE0 53 -#define A31_CLK_AHB1_FE1 54 -#define A31_CLK_AHB1_MP 55 -#define A31_CLK_AHB1_GPU 56 -#define A31_CLK_AHB1_DEU0 57 -#define A31_CLK_AHB1_DEU1 58 -#define A31_CLK_AHB1_DRC0 59 -#define A31_CLK_AHB1_DRC1 60 -#define A31_CLK_APB1_CODEC 61 -#define A31_CLK_APB1_SPDIF 62 *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***