From owner-freebsd-current@FreeBSD.ORG Fri Dec 9 04:30:34 2005 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 6A8A216A420 for ; Fri, 9 Dec 2005 04:30:34 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from speedfactory.net (mail6.speedfactory.net [66.23.216.219]) by mx1.FreeBSD.org (Postfix) with ESMTP id 344CC43D46 for ; Fri, 9 Dec 2005 04:30:24 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (unverified [66.23.211.162]) by speedfactory.net (SurgeMail 3.5b3) with ESMTP id 3427614 for multiple; Thu, 08 Dec 2005 23:32:18 -0500 Received: from zion.baldwin.cx (zion.baldwin.cx [192.168.0.7]) (authenticated bits=0) by server.baldwin.cx (8.13.1/8.13.1) with ESMTP id jB94U7Rg076451; Thu, 8 Dec 2005 23:30:09 -0500 (EST) (envelope-from jhb@freebsd.org) From: John Baldwin To: "Darren Pilgrim" Date: Thu, 8 Dec 2005 23:26:36 -0500 User-Agent: KMail/1.8.3 References: <000101c5fc28$f791b520$642a15ac@smiley> In-Reply-To: <000101c5fc28$f791b520$642a15ac@smiley> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Message-Id: <200512082326.37351.jhb@freebsd.org> X-Spam-Status: No, score=-2.8 required=4.2 tests=ALL_TRUSTED autolearn=failed version=3.0.2 X-Spam-Checker-Version: SpamAssassin 3.0.2 (2004-11-16) on server.baldwin.cx X-Server: High Performance Mail Server - http://surgemail.com r=1653887525 Cc: freebsd-current@freebsd.org Subject: Re: can someone explain...[ PCI interrupts] X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Dec 2005 04:30:34 -0000 On Thursday 08 December 2005 01:55 pm, Darren Pilgrim wrote: > From: John Baldwin > > > On Wednesday 07 December 2005 06:11 pm, Darren Pilgrim wrote: > > > What if the APIC was programmed to be edge-triggered just before the > > > ithread runs and programmed back to level-trigger when the ithread > > > completes? > > > > I'd rather work on my other solution which might be about 5 lines of co= de > > rather than screw around with the APICs when that might have other side > > effects. > > My apologies, I didn't intend to come off as dictating design. I'm > interested in the subject and it's rare to find people knowledgeable and > willing to converse about more advanced topics. > > Like many others here, I have a very significant investment in hardware to > which this directly relates. I wanted to find out about the details of t= he > behavior I'm observing and the impact of various solutions as both a > business man and a student of engineering. In fairness, Linux does seem to mess with the APICs this way (set to edge w= hen=20 an interrupt comes in and then reset it to level) to work around a bug on=20 some older I/O APICs. I'm not sure / can't remember if they do it for all= =20 PCI interrupts on APICs though. I need to look at the docs for the PXH=20 bridges in question again, but I think that when it does the legacy INTx=20 thing it is swizzling the interrupts to the bridge's INTx pins using the=20 standard PCI-PCI swizzle, in which case patching around the routing is a=20 simple patch of changing the $PIR and MPTable drivers to ignore such bridge= s=20 based on the devid, and changing the ACPI PCI-PCI bridge driver to ignore t= he=20 _PRT for such bridges. Fortunately, one of my recently added test machines= =20 reproduces the problem so I can test this idea and give people a patch that= =20 at least somewhat works for further testing. Maybe in a day or so. =2D-=20 John Baldwin =A0<>< =A0http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" =A0=3D =A0http://www.FreeBSD.org