Date: Sat, 19 Mar 2005 22:36:40 GMT From: Juli Mallett <jmallett@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 73546 for review Message-ID: <200503192236.j2JMaer8047887@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=73546 Change 73546 by jmallett@jmallett_windward on 2005/03/19 22:36:39 Remove r5k and mips32/mips64 cache support for now. As per usual, this is support I'll want later, but it helps to remove some clutter. Affected files ... .. //depot/projects/mips/sys/conf/files.mips#43 edit .. //depot/projects/mips/sys/mips/include/cache.h#2 edit .. //depot/projects/mips/sys/mips/include/cache_mipsNN.h#2 delete .. //depot/projects/mips/sys/mips/include/cache_r5k.h#3 delete .. //depot/projects/mips/sys/mips/include/mipsNN.h#2 delete .. //depot/projects/mips/sys/mips/mips/cache.c#8 edit .. //depot/projects/mips/sys/mips/mips/cache_mipsNN.c#3 delete .. //depot/projects/mips/sys/mips/mips/cache_r5k.c#5 delete .. //depot/projects/mips/sys/mips/mips/cache_r5k_subr.S#5 delete .. //depot/projects/mips/sys/mips/mips/machdep.c#53 edit Differences ... ==== //depot/projects/mips/sys/conf/files.mips#43 (text+ko) ==== @@ -34,10 +34,7 @@ mips/mips/vm_machdep.c standard # XXX cache code needs to be split up per CPU type, but yuck. mips/mips/cache.c standard -mips/mips/cache_mipsNN.c standard mips/mips/cache_r4k.c standard -mips/mips/cache_r5k.c standard -mips/mips/cache_r5k_subr.S standard mips/mips/db_disasm.c optional ddb mips/mips/db_hwwatch.c optional ddb ==== //depot/projects/mips/sys/mips/include/cache.h#2 (text+ko) ==== @@ -135,20 +135,11 @@ void (*mco_pdcache_wb_range)(vm_paddr_t, vm_size_t); /* These are called only by the (mipsNN) icache functions. */ - void (*mco_intern_pdcache_wbinv_all)(void); - void (*mco_intern_pdcache_wbinv_range_index)(vm_paddr_t, vm_size_t); - void (*mco_intern_pdcache_wb_range)(vm_paddr_t, vm_size_t); - void (*mco_sdcache_wbinv_all)(void); void (*mco_sdcache_wbinv_range)(vm_paddr_t, vm_size_t); void (*mco_sdcache_wbinv_range_index)(vm_paddr_t, vm_size_t); void (*mco_sdcache_inv_range)(vm_paddr_t, vm_size_t); void (*mco_sdcache_wb_range)(vm_paddr_t, vm_size_t); - - /* These are called only by the (mipsNN) icache functions. */ - void (*mco_intern_sdcache_wbinv_all)(void); - void (*mco_intern_sdcache_wbinv_range_index)(vm_paddr_t, vm_size_t); - void (*mco_intern_sdcache_wb_range)(vm_paddr_t, vm_size_t); }; extern struct mips_cache_ops mips_cache_ops; @@ -199,11 +190,6 @@ extern u_int mips_cache_alias_mask; extern u_int mips_cache_prefer_mask; -/* - * XXX XXX XXX THIS SHOULD NOT EXIST XXX XXX XXX - */ -#define mips_cache_indexof(x) (((vm_paddr_t)(x)) & mips_cache_alias_mask) - #define __mco_noargs(prefix, x) \ do { \ (*mips_cache_ops.mco_ ## prefix ## p ## x )(); \ @@ -242,21 +228,5 @@ #define mips_dcache_wb_range(v, s) \ __mco_2args(, dcache_wb_range, (v), (s)) - -/* - * Private D-cache functions only called from (currently only the - * mipsNN) I-cache functions. - */ -#define mips_intern_dcache_wbinv_all() \ - __mco_noargs(intern_, dcache_wbinv_all) - -#define mips_intern_dcache_wbinv_range_index(v, s) \ - __mco_2args(intern_, dcache_wbinv_range_index, (v), (s)) - -#define mips_intern_dcache_wb_range(v, s) \ - __mco_2args(intern_, dcache_wb_range, (v), (s)) - void mips_config_cache(void); void mips_dcache_compute_align(void); - -#include <machine/cache_mipsNN.h> ==== //depot/projects/mips/sys/mips/mips/cache.c#8 (text+ko) ==== @@ -76,11 +76,7 @@ #include <machine/locore.h> #include <machine/cache_r4k.h> -#include <machine/cache_r5k.h> -#include <machine/mipsNN.h> /* MIPS32/MIPS64 registers */ -#include <machine/cache_mipsNN.h> - /* PRIMARY CACHE VARIABLES */ u_int mips_picache_size; u_int mips_picache_line_size; @@ -231,24 +227,6 @@ * Configure primary caches. */ switch (MIPS_PRID_IMPL(cpu_id)) { - case MIPS_R4100: - /* - * R4100 (NEC VR series) revision number means: - * - * MIPS_PRID_REV_MAJ MIPS_PRID_REV_MIN - * VR4102 4 ? - * VR4111 5 ? - * VR4181 5 ? - * VR4121 6 ? - * VR4122 7 0 or 1 - * VR4181A 7 3 < - * VR4131 8 ? - */ - /* Vr4131 has R4600 style 2-way set-associative cache */ - if (MIPS_PRID_REV_MAJ(cpu_id) == 8) - goto primary_cache_is_2way; - /* FALLTHROUGH */ - case MIPS_R4000: case MIPS_R4300: mips_picache_ways = 1; @@ -316,102 +294,6 @@ /* Virtually-indexed cache; no use for colors. */ break; - case MIPS_R4600: -#ifdef ENABLE_MIPS_R4700 - case MIPS_R4700: -#endif -#ifndef ENABLE_MIPS_R3NKK - case MIPS_R5000: -#endif - case MIPS_RM5200: -primary_cache_is_2way: - mips_picache_ways = 2; - mips_pdcache_ways = 2; - - mips3_get_cache_config(csizebase); - - switch (mips_picache_line_size) { - case 32: - mips_cache_ops.mco_icache_sync_all = - r5k_icache_sync_all_32; - mips_cache_ops.mco_icache_sync_range = - r5k_icache_sync_range_32; - mips_cache_ops.mco_icache_sync_range_index = - r5k_icache_sync_range_index_32; - break; - - default: - panic("r5k picache line size %d", - mips_picache_line_size); - } - - switch (mips_pdcache_line_size) { - case 16: - mips_cache_ops.mco_pdcache_wbinv_all = - r5k_pdcache_wbinv_all_16; - mips_cache_ops.mco_pdcache_wbinv_range = - r5k_pdcache_wbinv_range_16; - mips_cache_ops.mco_pdcache_wbinv_range_index = - r5k_pdcache_wbinv_range_index_16; - mips_cache_ops.mco_pdcache_inv_range = - r5k_pdcache_inv_range_16; - mips_cache_ops.mco_pdcache_wb_range = - r5k_pdcache_wb_range_16; - break; - - case 32: - mips_cache_ops.mco_pdcache_wbinv_all = - r5k_pdcache_wbinv_all_32; - mips_cache_ops.mco_pdcache_wbinv_range = - r5k_pdcache_wbinv_range_32; - mips_cache_ops.mco_pdcache_wbinv_range_index = - r5k_pdcache_wbinv_range_index_32; - mips_cache_ops.mco_pdcache_inv_range = - r5k_pdcache_inv_range_32; - mips_cache_ops.mco_pdcache_wb_range = - r5k_pdcache_wb_range_32; - break; - - default: - panic("r5k pdcache line size %d", - mips_pdcache_line_size); - } - - /* - * Deal with R4600 chip bugs. - */ - if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 && - MIPS_PRID_REV_MAJ(cpu_id) == 1) { - KASSERT(mips_pdcache_line_size == 32, ("line size 32")); - mips_cache_ops.mco_pdcache_wbinv_range = - r4600v1_pdcache_wbinv_range_32; - mips_cache_ops.mco_pdcache_inv_range = - r4600v1_pdcache_inv_range_32; - mips_cache_ops.mco_pdcache_wb_range = - r4600v1_pdcache_wb_range_32; - } else if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4600 && - MIPS_PRID_REV_MAJ(cpu_id) == 2) { - KASSERT(mips_pdcache_line_size == 32, ("line size 32")); - mips_cache_ops.mco_pdcache_wbinv_range = - r4600v2_pdcache_wbinv_range_32; - mips_cache_ops.mco_pdcache_inv_range = - r4600v2_pdcache_inv_range_32; - mips_cache_ops.mco_pdcache_wb_range = - r4600v2_pdcache_wb_range_32; - } - - /* - * Deal with VR4131 chip bugs. - */ - if (MIPS_PRID_IMPL(cpu_id) == MIPS_R4100 && - MIPS_PRID_REV_MAJ(cpu_id) == 8) { - KASSERT(mips_pdcache_line_size == 16, ("line size 16")); - mips_cache_ops.mco_pdcache_wbinv_range = - vr4131v1_pdcache_wbinv_range_16; - } - - /* Virtually-indexed cache; no use for colors. */ - break; default: panic("can't handle primary cache on impl 0x%x", MIPS_PRID_IMPL(cpu_id)); @@ -510,22 +392,6 @@ mips_sdcache_ways, mips_sdcache_line_size); } break; -#ifndef ENABLE_MIPS_R3NKK - case MIPS_R5000: -#endif - case MIPS_RM5200: - mips_cache_ops.mco_sdcache_wbinv_all = - r5k_sdcache_wbinv_all; - mips_cache_ops.mco_sdcache_wbinv_range = - r5k_sdcache_wbinv_range; - mips_cache_ops.mco_sdcache_wbinv_range_index = - r5k_sdcache_wbinv_rangeall; /* XXX? */ - mips_cache_ops.mco_sdcache_inv_range = - r5k_sdcache_wbinv_range; - mips_cache_ops.mco_sdcache_wb_range = - r5k_sdcache_wb_range; - break; - default: panic("can't handle secondary cache on impl 0x%x", MIPS_PRID_IMPL(cpu_id)); @@ -559,7 +425,6 @@ void mips3_get_cache_config(int csizebase) { - int has_sdcache_enable = 0; uint32_t config; config = mips_rd_config(); @@ -579,15 +444,6 @@ mips_cache_prefer_mask = max(mips_pdcache_size, mips_picache_size) - 1; - switch(MIPS_PRID_IMPL(cpu_id)) { -#ifndef ENABLE_MIPS_R3NKK - case MIPS_R5000: -#endif - case MIPS_RM5200: - has_sdcache_enable = 1; - break; - } - /* * If CPU has a software-enabled L2 cache, check both if it's * present and if it's enabled before making assumptions the @@ -595,17 +451,7 @@ * as if there were no L2 cache. */ if ((config & MIPS_CONFIG_SC) == 0) { - if (has_sdcache_enable == 0 || - (has_sdcache_enable && (config & MIPS_CONFIG_SE))) { - mips_sdcache_line_size = - MIPS_CONFIG_CACHE_L2_LSIZE(config); - if ((config & MIPS_CONFIG_SS) == 0) - mips_scache_unified = 1; - } else { -#ifdef CACHE_DEBUG - printf("External cache detected, but is disabled -- WILL NOT ENABLE!\n"); -#endif /* CACHE_DEBUG */ - } + printf("External cache detected, but is disabled -- WILL NOT ENABLE!\n"); } } ==== //depot/projects/mips/sys/mips/mips/machdep.c#53 (text+ko) ==== @@ -56,7 +56,6 @@ #include <machine/hwfunc.h> #include <machine/locore.h> #include <machine/md_var.h> -#include <machine/mipsNN.h> #include <machine/pte.h> #include <machine/tlb.h>
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