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Date:      Mon, 26 Mar 2012 03:55:45 +0000 (UTC)
From:      Pyun YongHyeon <yongari@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-8@freebsd.org
Subject:   svn commit: r233490 - in stable/8/sys: dev/re i386/conf pci
Message-ID:  <201203260355.q2Q3tjEY013362@svn.freebsd.org>

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Author: yongari
Date: Mon Mar 26 03:55:45 2012
New Revision: 233490
URL: http://svn.freebsd.org/changeset/base/233490

Log:
  MFC r232145:
    Use correct Config registers for RTL8139 family. Unlike RTL8168 and
    RTL810x family , RTL8139 has different register map for Config
    registers.
  
    While here, follow the lead of re(4) in WOL configuration.
     - Disable WOL_UCAST and WOL_MCAST capabilities by default.
     - Config5 register write does not need to unlock EEPROM access
       on RTL8139 family but unlocking EEPROM access does not affect
       its operation and make it consistent with re(4).
  
    Reported by:	Matt Renzelmann  mjr <> cs dot wisc dot edu

Modified:
  stable/8/sys/dev/re/if_re.c
  stable/8/sys/pci/if_rl.c
  stable/8/sys/pci/if_rlreg.h
Directory Properties:
  stable/8/sys/   (props changed)
  stable/8/sys/amd64/include/xen/   (props changed)
  stable/8/sys/boot/   (props changed)
  stable/8/sys/cddl/contrib/opensolaris/   (props changed)
  stable/8/sys/contrib/dev/acpica/   (props changed)
  stable/8/sys/contrib/pf/   (props changed)
  stable/8/sys/dev/e1000/   (props changed)
  stable/8/sys/i386/conf/XENHVM   (props changed)

Modified: stable/8/sys/dev/re/if_re.c
==============================================================================
--- stable/8/sys/dev/re/if_re.c	Mon Mar 26 03:54:19 2012	(r233489)
+++ stable/8/sys/dev/re/if_re.c	Mon Mar 26 03:55:45 2012	(r233490)
@@ -1473,6 +1473,22 @@ re_attach(device_t dev)
 		break;
 	}
 
+	if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) {
+		sc->rl_cfg0 = RL_8139_CFG0;
+		sc->rl_cfg1 = RL_8139_CFG1;
+		sc->rl_cfg2 = 0;
+		sc->rl_cfg3 = RL_8139_CFG3;
+		sc->rl_cfg4 = RL_8139_CFG4;
+		sc->rl_cfg5 = RL_8139_CFG5;
+	} else {
+		sc->rl_cfg0 = RL_CFG0;
+		sc->rl_cfg1 = RL_CFG1;
+		sc->rl_cfg2 = RL_CFG2;
+		sc->rl_cfg3 = RL_CFG3;
+		sc->rl_cfg4 = RL_CFG4;
+		sc->rl_cfg5 = RL_CFG5;
+	}
+
 	/* Reset the adapter. */
 	RL_LOCK(sc);
 	re_reset(sc);
@@ -1480,12 +1496,12 @@ re_attach(device_t dev)
 
 	/* Enable PME. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
-	cfg = CSR_READ_1(sc, RL_CFG1);
+	cfg = CSR_READ_1(sc, sc->rl_cfg1);
 	cfg |= RL_CFG1_PME;
-	CSR_WRITE_1(sc, RL_CFG1, cfg);
-	cfg = CSR_READ_1(sc, RL_CFG5);
+	CSR_WRITE_1(sc, sc->rl_cfg1, cfg);
+	cfg = CSR_READ_1(sc, sc->rl_cfg5);
 	cfg &= RL_CFG5_PME_STS;
-	CSR_WRITE_1(sc, RL_CFG5, cfg);
+	CSR_WRITE_1(sc, sc->rl_cfg5, cfg);
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
 	if ((sc->rl_flags & RL_FLAG_PAR) != 0) {
@@ -2908,32 +2924,32 @@ re_set_jumbo(struct rl_softc *sc, int ju
 
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG);
 	if (jumbo != 0) {
-		CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) |
+		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) |
 		    RL_CFG3_JUMBO_EN0);
 		switch (sc->rl_hwrev->rl_rev) {
 		case RL_HWREV_8168DP:
 			break;
 		case RL_HWREV_8168E:
-			CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
-			    0x01);
+			CSR_WRITE_1(sc, sc->rl_cfg4,
+			    CSR_READ_1(sc, sc->rl_cfg4) | 0x01);
 			break;
 		default:
-			CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) |
-			    RL_CFG4_JUMBO_EN1);
+			CSR_WRITE_1(sc, sc->rl_cfg4,
+			    CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1);
 		}
 	} else {
-		CSR_WRITE_1(sc, RL_CFG3, CSR_READ_1(sc, RL_CFG3) &
+		CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) &
 		    ~RL_CFG3_JUMBO_EN0);
 		switch (sc->rl_hwrev->rl_rev) {
 		case RL_HWREV_8168DP:
 			break;
 		case RL_HWREV_8168E:
-			CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
-			    ~0x01);
+			CSR_WRITE_1(sc, sc->rl_cfg4,
+			    CSR_READ_1(sc, sc->rl_cfg4) & ~0x01);
 			break;
 		default:
-			CSR_WRITE_1(sc, RL_CFG4, CSR_READ_1(sc, RL_CFG4) &
-			    ~RL_CFG4_JUMBO_EN1);
+			CSR_WRITE_1(sc, sc->rl_cfg4,
+			    CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1);
 		}
 	}
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
@@ -3046,7 +3062,7 @@ re_init_locked(struct rl_softc *sc)
 	if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC ||
 	    sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) {
 		reg = 0x000fff00;
-		if ((CSR_READ_1(sc, RL_CFG2) & RL_CFG2_PCI66MHZ) != 0)
+		if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0)
 			reg |= 0x000000ff;
 		if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE)
 			reg |= 0x00f00000;
@@ -3211,7 +3227,8 @@ re_init_locked(struct rl_softc *sc)
 	if (sc->rl_testmode)
 		return;
 
-	CSR_WRITE_1(sc, RL_CFG1, CSR_READ_1(sc, RL_CFG1) | RL_CFG1_DRVLOAD);
+	CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) |
+	    RL_CFG1_DRVLOAD);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
@@ -3744,19 +3761,19 @@ re_setwol(struct rl_softc *sc)
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 
 	/* Enable PME. */
-	v = CSR_READ_1(sc, RL_CFG1);
+	v = CSR_READ_1(sc, sc->rl_cfg1);
 	v &= ~RL_CFG1_PME;
 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
 		v |= RL_CFG1_PME;
-	CSR_WRITE_1(sc, RL_CFG1, v);
+	CSR_WRITE_1(sc, sc->rl_cfg1, v);
 
-	v = CSR_READ_1(sc, RL_CFG3);
+	v = CSR_READ_1(sc, sc->rl_cfg3);
 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 		v |= RL_CFG3_WOL_MAGIC;
-	CSR_WRITE_1(sc, RL_CFG3, v);
+	CSR_WRITE_1(sc, sc->rl_cfg3, v);
 
-	v = CSR_READ_1(sc, RL_CFG5);
+	v = CSR_READ_1(sc, sc->rl_cfg5);
 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST |
 	    RL_CFG5_WOL_LANWAKE);
 	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
@@ -3765,7 +3782,7 @@ re_setwol(struct rl_softc *sc)
 		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
 		v |= RL_CFG5_WOL_LANWAKE;
-	CSR_WRITE_1(sc, RL_CFG5, v);
+	CSR_WRITE_1(sc, sc->rl_cfg5, v);
 
 	/* Config register write done. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
@@ -3801,17 +3818,17 @@ re_clrwol(struct rl_softc *sc)
 	/* Enable config register write. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 
-	v = CSR_READ_1(sc, RL_CFG3);
+	v = CSR_READ_1(sc, sc->rl_cfg3);
 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
-	CSR_WRITE_1(sc, RL_CFG3, v);
+	CSR_WRITE_1(sc, sc->rl_cfg3, v);
 
 	/* Config register write done. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
-	v = CSR_READ_1(sc, RL_CFG5);
+	v = CSR_READ_1(sc, sc->rl_cfg5);
 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
 	v &= ~RL_CFG5_WOL_LANWAKE;
-	CSR_WRITE_1(sc, RL_CFG5, v);
+	CSR_WRITE_1(sc, sc->rl_cfg5, v);
 }
 
 static void

Modified: stable/8/sys/pci/if_rl.c
==============================================================================
--- stable/8/sys/pci/if_rl.c	Mon Mar 26 03:54:19 2012	(r233489)
+++ stable/8/sys/pci/if_rl.c	Mon Mar 26 03:55:45 2012	(r233490)
@@ -717,6 +717,13 @@ rl_attach(device_t dev)
 		goto fail;
 	}
 
+	sc->rl_cfg0 = RL_8139_CFG0;
+	sc->rl_cfg1 = RL_8139_CFG1;
+	sc->rl_cfg2 = 0;
+	sc->rl_cfg3 = RL_8139_CFG3;
+	sc->rl_cfg4 = RL_8139_CFG4;
+	sc->rl_cfg5 = RL_8139_CFG5;
+
 	/*
 	 * Reset the adapter. Only take the lock here as it's needed in
 	 * order to call rl_reset().
@@ -818,6 +825,7 @@ rl_attach(device_t dev)
 		}
 	}
 	ifp->if_capenable = ifp->if_capabilities;
+	ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST);
 #ifdef DEVICE_POLLING
 	ifp->if_capabilities |= IFCAP_POLLING;
 #endif
@@ -1754,7 +1762,7 @@ rl_init_locked(struct rl_softc *sc)
 	sc->rl_flags &= ~RL_FLAG_LINK;
 	mii_mediachg(mii);
 
-	CSR_WRITE_1(sc, RL_CFG1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
+	CSR_WRITE_1(sc, sc->rl_cfg1, RL_CFG1_DRVLOAD|RL_CFG1_FULLDUPLEX);
 
 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
@@ -2055,22 +2063,19 @@ rl_setwol(struct rl_softc *sc)
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 
 	/* Enable PME. */
-	v = CSR_READ_1(sc, RL_CFG1);
+	v = CSR_READ_1(sc, sc->rl_cfg1);
 	v &= ~RL_CFG1_PME;
 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
 		v |= RL_CFG1_PME;
-	CSR_WRITE_1(sc, RL_CFG1, v);
+	CSR_WRITE_1(sc, sc->rl_cfg1, v);
 
-	v = CSR_READ_1(sc, RL_CFG3);
+	v = CSR_READ_1(sc, sc->rl_cfg3);
 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
 		v |= RL_CFG3_WOL_MAGIC;
-	CSR_WRITE_1(sc, RL_CFG3, v);
-
-	/* Config register write done. */
-	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+	CSR_WRITE_1(sc, sc->rl_cfg3, v);
 
-	v = CSR_READ_1(sc, RL_CFG5);
+	v = CSR_READ_1(sc, sc->rl_cfg5);
 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
 	v &= ~RL_CFG5_WOL_LANWAKE;
 	if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0)
@@ -2079,7 +2084,11 @@ rl_setwol(struct rl_softc *sc)
 		v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST;
 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
 		v |= RL_CFG5_WOL_LANWAKE;
-	CSR_WRITE_1(sc, RL_CFG5, v);
+	CSR_WRITE_1(sc, sc->rl_cfg5, v);
+
+	/* Config register write done. */
+	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
+
 	/* Request PME if WOL is requested. */
 	pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2);
 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
@@ -2101,15 +2110,15 @@ rl_clrwol(struct rl_softc *sc)
 	/* Enable config register write. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE);
 
-	v = CSR_READ_1(sc, RL_CFG3);
+	v = CSR_READ_1(sc, sc->rl_cfg3);
 	v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC);
-	CSR_WRITE_1(sc, RL_CFG3, v);
+	CSR_WRITE_1(sc, sc->rl_cfg3, v);
 
 	/* Config register write done. */
 	CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF);
 
-	v = CSR_READ_1(sc, RL_CFG5);
+	v = CSR_READ_1(sc, sc->rl_cfg5);
 	v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST);
 	v &= ~RL_CFG5_WOL_LANWAKE;
-	CSR_WRITE_1(sc, RL_CFG5, v);
+	CSR_WRITE_1(sc, sc->rl_cfg5, v);
 }

Modified: stable/8/sys/pci/if_rlreg.h
==============================================================================
--- stable/8/sys/pci/if_rlreg.h	Mon Mar 26 03:54:19 2012	(r233489)
+++ stable/8/sys/pci/if_rlreg.h	Mon Mar 26 03:55:45 2012	(r233490)
@@ -74,6 +74,14 @@
 #define	RL_TIMERCNT	0x0048		/* timer count register */
 #define	RL_MISSEDPKT	0x004C		/* missed packet counter */
 #define	RL_EECMD	0x0050		/* EEPROM command register */
+
+/* RTL8139/RTL8139C+ only */
+#define	RL_8139_CFG0	0x0051		/* config register #0 */
+#define	RL_8139_CFG1	0x0052		/* config register #1 */
+#define	RL_8139_CFG3	0x0059		/* config register #3 */
+#define	RL_8139_CFG4	0x005A		/* config register #4 */
+#define	RL_8139_CFG5	0x00D8		/* config register #5 */
+
 #define	RL_CFG0		0x0051		/* config register #0 */
 #define	RL_CFG1		0x0052		/* config register #1 */
 #define	RL_CFG2		0x0053		/* config register #2 */
@@ -873,6 +881,12 @@ struct rl_softc {
 	int			rl_eewidth;
 	int			rl_expcap;
 	int			rl_txthresh;
+	bus_size_t		rl_cfg0;
+	bus_size_t		rl_cfg1;
+	bus_size_t		rl_cfg2;
+	bus_size_t		rl_cfg3;
+	bus_size_t		rl_cfg4;
+	bus_size_t		rl_cfg5;
 	struct rl_chain_data	rl_cdata;
 	struct rl_list_data	rl_ldata;
 	struct callout		rl_stat_callout;



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