NTEK_FCR,
+			  UFINTEK_FCR_EN | UFINTEK_FCR_TRIGGER_8);
+
+	sc->sc_mcr =  UFINTEK_MCR_DTR|UFINTEK_MCR_RTS;
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_MCR, sc->sc_mcr);
+	
+	/* Enable interrupts */
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_IER,
+			  UFINTEK_IER_MSI );
+}
+
+static void
+ufintek_cfg_close(struct ucom_softc *ucom)
+{
+	return;
+}
+
+static void
+ufintek_cfg_set_break(struct ucom_softc *ucom, uint8_t onoff)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+
+	if (onoff)
+		sc->sc_lcr |= UFINTEK_LCR_BREAK;
+	else
+		sc->sc_lcr &= ~UFINTEK_LCR_BREAK;
+
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_LCR, sc->sc_lcr);
+}
+
+static void
+ufintek_cfg_set_dtr(struct ucom_softc *ucom, uint8_t onoff)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+
+	if (onoff)
+		sc->sc_mcr |= UFINTEK_MCR_DTR;
+	else
+		sc->sc_mcr &= ~UFINTEK_MCR_DTR;
+
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_MCR, sc->sc_mcr);
+}
+
+static void
+ufintek_cfg_set_rts(struct ucom_softc *ucom, uint8_t onoff)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+
+	if (onoff)
+		sc->sc_mcr |= UFINTEK_MCR_RTS;
+	else
+		sc->sc_mcr &= ~UFINTEK_MCR_RTS;
+
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_MCR, sc->sc_mcr);
+}
+
+static int
+ufintek_pre_param(struct ucom_softc *ucom, struct termios *t)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+	uint16_t divisor;
+
+	if ((t->c_ospeed <= 1) || (t->c_ospeed > 115200))
+		return (EINVAL);
+
+	sc->sc_mcr = UFINTEK_MCR_DTR|UFINTEK_MCR_RTS;
+	sc->sc_lcr = UFINTEK_DEFAULT_LCR;
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_LCR, sc->sc_lcr);
+
+	DPRINTF("baud=%d\n", t->c_ospeed);
+	
+	divisor = ((uint32_t)UFINTEK_BAUD_REF) / ((uint32_t)t->c_ospeed);
+
+	if (divisor == 0) {
+		DPRINTF("invalid baud rate!\n");
+		return (1);
+	}
+
+	/* Flip RXBUF and TXBUF to BAUDLO and BAUDHI */
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_LCR, UFINTEK_LCR_DLAB);
+        ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_BAUDLO,
+			  (divisor & 0xFF));
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_BAUDHI,
+			  ((divisor >> 8) & 0xFF));
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_LCR, sc->sc_lcr);
+	
+	return (0);
+}
+
+static void
+ufintek_cfg_param(struct ucom_softc *ucom, struct termios *t)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+	uint8_t lcr=0;
+	uint16_t divisor;
+	
+	DPRINTF("baud=%d\n", t->c_ospeed);
+	
+	divisor = ((uint32_t)UFINTEK_BAUD_REF) / ((uint32_t)t->c_ospeed);
+
+	if (divisor == 0) {
+		DPRINTF("invalid baud rate!\n");
+		return;
+	}
+
+	/* Flip RXBUF and TXBUF to BAUDLO and BAUDHI */
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_LCR, UFINTEK_LCR_DLAB);
+        ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_BAUDLO,
+			  (divisor & 0xFF));
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_BAUDHI,
+			  ((divisor >> 8) & 0xFF));
+
+	if (!(t->c_cflag & CIGNORE)) {
+		lcr = 0;
+		switch (t->c_cflag & CSIZE) {
+		case CS8:
+			lcr |= UFINTEK_LCR_WORDLEN_8;
+			break;
+		case CS7:
+			lcr |= UFINTEK_LCR_WORDLEN_7;
+			break;
+		case CS6:
+			lcr |= UFINTEK_LCR_WORDLEN_6;
+			break;
+		case CS5:
+			break;
+		default:
+			break;
+		}
+
+		if (t->c_cflag & CSTOPB)
+			lcr |= UFINTEK_LCR_STOP_BITS_1;
+		if (t->c_cflag & PARODD)
+			lcr |= UFINTEK_LCR_PARITY_ODD;
+		else if (t->c_cflag & PARENB)
+			lcr |= UFINTEK_LCR_PARITY_EVEN;
+	}
+	sc->sc_lcr = lcr;
+	ufintek_cfg_write(sc, UFINTEK_UART_REG | UFINTEK_LCR, sc->sc_lcr);
+}
+
+static void
+ufintek_cfg_get_status(struct ucom_softc *ucom, uint8_t *p_lsr, uint8_t *p_msr)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+	uint8_t lsr;
+	uint8_t ufintek_msr;
+	
+	lsr = ufintek_cfg_read(sc, UFINTEK_UART_REG | UFINTEK_LSR);
+	lsr &= 7;	/* Only need bottom bits */
+	*p_lsr = lsr;
+	
+	ufintek_msr = ufintek_cfg_read(sc, UFINTEK_UART_REG | UFINTEK_MSR);
+
+	/* translate bits */
+
+	*p_msr = 0;
+	if (ufintek_msr & UFINTEK_MSR_CTS)
+		*p_msr |= SER_CTS;
+
+	if (ufintek_msr & UFINTEK_MSR_CD)
+		*p_msr |= SER_DCD;
+
+	if (ufintek_msr & UFINTEK_MSR_RI)
+		*p_msr |= SER_RI;
+
+	if (ufintek_msr & UFINTEK_MSR_RTS)
+		*p_msr |= SER_RTS;
+}
+
+static void
+ufintek_start_read(struct ucom_softc *ucom)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+
+	usbd_transfer_start(sc->sc_xfer[UFINTEK_BULK_DT_RD]);
+}
+
+static void
+ufintek_stop_read(struct ucom_softc *ucom)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+
+	usbd_transfer_stop(sc->sc_xfer[UFINTEK_BULK_DT_RD]);
+}
+
+static void
+ufintek_start_write(struct ucom_softc *ucom)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+
+	usbd_transfer_start(sc->sc_xfer[UFINTEK_BULK_DT_WR]);
+}
+
+static void
+ufintek_stop_write(struct ucom_softc *ucom)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+
+	usbd_transfer_stop(sc->sc_xfer[UFINTEK_BULK_DT_WR]);
+}
+
+static void
+ufintek_cfg_write(struct ufintek_softc *sc, uint16_t reg, uint8_t val)
+{
+	struct usb_device_request req;
+	usb_error_t uerr;
+	uint8_t data;
+	
+	req.bmRequestType = UFINTEK_WRITE;
+	req.bRequest = UFINTEK_REGISTER_REQUEST;
+	USETW(req.wValue, reg);
+	USETW(req.wIndex, 0);
+	USETW(req.wLength, 1);
+
+	data = val;
+
+	uerr = ucom_cfg_do_request(sc->sc_udev, &sc->sc_ucom,
+		&req, &data, 0, 1000);
+	if (uerr != 0)
+		DPRINTF("failed to set ctrl %s\n", usbd_errstr(uerr));
+}
+
+static uint8_t
+ufintek_cfg_read(struct ufintek_softc *sc, uint16_t reg)
+{
+	struct usb_device_request req;
+	uint8_t val;
+	
+	req.bmRequestType = UFINTEK_READ;
+	req.bRequest = UFINTEK_REGISTER_REQUEST;
+	USETW(req.wValue, reg);
+	USETW(req.wIndex, 0);
+	USETW(req.wLength, 1);
+
+	ucom_cfg_do_request(sc->sc_udev, &sc->sc_ucom, 
+	    &req, &val, 0, 1000);
+
+	DPRINTF("reg=0x%04x, val=0x%02x\n", reg, val);
+	return (val);
+}
+
+
+static void
+ufintek_write_callback(struct usb_xfer *xfer, usb_error_t error)
+{
+	struct ufintek_softc *sc = usbd_xfer_softc(xfer);
+	struct usb_page_cache *pc;
+	uint32_t actlen;
+
+	switch (USB_GET_STATE(xfer)) {
+	case USB_ST_SETUP:
+	case USB_ST_TRANSFERRED:
+tr_setup:
+
+		pc = usbd_xfer_get_frame(xfer, 0);
+		if (ucom_get_data(&sc->sc_ucom, pc, 0,
+			UFINTEK_BUFSIZE, &actlen)) {
+			usbd_xfer_set_frame_len(xfer, 0, actlen);
+			usbd_transfer_submit(xfer);
+		}
+		return;
+
+	default:			/* Error */
+		if (error != USB_ERR_CANCELLED) {
+			/* try to clear stall first */
+			usbd_xfer_set_stall(xfer);
+			goto tr_setup;
+		}
+		return;
+	}
+}
+
+static void
+ufintek_read_callback(struct usb_xfer *xfer, usb_error_t error)
+{
+	struct ufintek_softc *sc = usbd_xfer_softc(xfer);
+	struct usb_page_cache *pc;
+	int actlen;
+	uint8_t buf[UFINTEK_BUFSIZE];
+	int i;
+	
+	usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
+	switch (USB_GET_STATE(xfer)) {
+	case USB_ST_TRANSFERRED:
+		DPRINTF("got %d bytes\n", actlen);
+		if ((actlen < 2) || (actlen % 2))
+			goto tr_setup;
+		pc = usbd_xfer_get_frame(xfer, 0);
+		usbd_copy_out(pc, 0, &buf, sizeof(buf));
+		/* XXX From Linux driver the very first byte after open
+		 * is supposed to be a status which we should ignore.
+		 * Why it is 0xFF I don't know TBH. 
+		 */
+		if (buf[0] == 0xFF) 
+			buf[0] = ufintek_cfg_read(sc, UFINTEK_UART_REG);
+		else {
+		/*
+		 * Annoyingly this device presents data as
+		 * <LSR><DATA><LSR><DATA> ...
+		 */
+		for (i = 0; i < actlen; i += 2) {
+			ucom_put_data(&sc->sc_ucom, pc, i+1, 1);
+		}
+
+		/* FALLTHROUGH */
+		}
+	case USB_ST_SETUP:
+tr_setup:
+		usbd_xfer_set_frame_len(xfer, 0, usbd_xfer_max_len(xfer));
+		usbd_transfer_submit(xfer);
+		return;
+
+	default:			/* Error */
+		if (error != USB_ERR_CANCELLED) {
+			/* try to clear stall first */
+			usbd_xfer_set_stall(xfer);
+			goto tr_setup;
+		}
+		return;
+	}
+}
+
+
+
+static void
+ufintek_poll(struct ucom_softc *ucom)
+{
+	struct ufintek_softc *sc = ucom->sc_parent;
+	usbd_transfer_poll(sc->sc_xfer, UFINTEK_N_TRANSFER);
+}
diff --git a/sys/modules/ufintek/Makefile b/sys/modules/ufintek/Makefile
new file mode 100644
index 000000000000..8156205fdfd4
--- /dev/null
+++ b/sys/modules/ufintek/Makefile
@@ -0,0 +1,37 @@
+#-
+# SPDX-License-Identifier: BSD-2-Clause
+#
+# Copyright (c) 2025 Diane Bruce
+# All rights reserved
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in the
+#    documentation and/or other materials provided with the distribution.
+#
+# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+# SUCH DAMAGE.
+#
+
+S=     ${SRCTOP}/sys
+
+.PATH: $S/dev/usb/serial
+
+KMOD=	ufintek
+SRCS=	opt_bus.h opt_usb.h device_if.h bus_if.h usb_if.h usbdevs.h \
+	ufintek.c
+
+.include <bsd.kmod.mk>