Date: Sat, 17 Aug 2019 23:52:17 +0000 (UTC) From: Niclas Zeising <zeising@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r509186 - head/cad/iverilog Message-ID: <201908172352.x7HNqHhA088774@repo.freebsd.org>
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Author: zeising Date: Sat Aug 17 23:52:17 2019 New Revision: 509186 URL: https://svnweb.freebsd.org/changeset/ports/509186 Log: cat/iverilog: Update to 10.3 Modified: head/cad/iverilog/Makefile head/cad/iverilog/distinfo Modified: head/cad/iverilog/Makefile ============================================================================== --- head/cad/iverilog/Makefile Sat Aug 17 23:51:04 2019 (r509185) +++ head/cad/iverilog/Makefile Sat Aug 17 23:52:17 2019 (r509186) @@ -2,8 +2,7 @@ # $FreeBSD$ PORTNAME= iverilog -PORTVERSION= 10.2 -PORTREVISION= 1 +PORTVERSION= 10.3 CATEGORIES= cad MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v10/ DISTNAME= verilog-${PORTVERSION} Modified: head/cad/iverilog/distinfo ============================================================================== --- head/cad/iverilog/distinfo Sat Aug 17 23:51:04 2019 (r509185) +++ head/cad/iverilog/distinfo Sat Aug 17 23:52:17 2019 (r509186) @@ -1,3 +1,3 @@ -TIMESTAMP = 1508676832 -SHA256 (verilog-10.2.tar.gz) = 96dedbddb12d375edb45a144a926a3ba1e3e138d6598b18e7d79f2ae6de9e500 -SIZE (verilog-10.2.tar.gz) = 1695227 +TIMESTAMP = 1566058481 +SHA256 (verilog-10.3.tar.gz) = 86bd45e7e12d1bc8772c3cdd394e68a9feccb2a6d14aaf7dae0773b7274368ef +SIZE (verilog-10.3.tar.gz) = 1698889
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