Date: Thu, 04 Nov 1999 18:03:36 -0800 From: Darryl Okahata <darrylo@sr.hp.com> To: freebsd-smp@FreeBSD.ORG Subject: Re: Dual Celeron + FreeBSD? Message-ID: <199911050203.SAA04671@mina.sr.hp.com> In-Reply-To: Your message of "Thu, 04 Nov 1999 16:01:33 PST." <199911050001.QAA51143@gndrsh.dnsmgr.net>
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"Rodney W. Grimes" <freebsd@gndrsh.dnsmgr.net> wrote:
> They do not have to be the same stepping, they must be MP comptabile
> steppings per the Intel Processor Errata Data Sheet. This applies
> to all Intel MP capible processors, from the P54 (Pentium) to the
> PIII Xeon.
>
> Some combinations work, others do not.
>
> Also they _should_ be MP tested chips, which can be determined by
> the S-spec number and other markings on the chip. On Pentium in
> is the last letter of the markings like SSS or VSS or VSU, last
> letter being U means only tested for UP operation, last letter
> being S means tested for MP operation.
Uh, the posters are talking about *Celerons*.
Celerons are not supported for SMP operation, and are probably not
even tested for SMP, although many (most? all???) happen to work in an
SMP configuration. It's somewhat like overclocking: if it works, great --
if it doesn't, don't expect much support (Intel won't support it, and
there's precious little help here).
Also, a rumor has been ongoing (for weeks) where, supposedly, Intel
is "fixing" the Celeron such that it will no longer operate in SMP mode.
These days, I'm not sure dual Celerons make sense. Unless you
overclock (which I don't recommend, for all the usual reasons), you're
only saving, oh, US$200-$230 compared to a comparable Pentium II-based
system. Also, because of the small 128K L2 cache and the 66MHz bus (no
overclocking, remember?), dual Celerons aren't as fast as dual P2s.
--
Darryl Okahata
darrylo@sr.hp.com
DISCLAIMER: this message is the author's personal opinion and does not
constitute the support, opinion, or policy of Agilent Technologies, or
of the little green men that have been following him all day.
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