From owner-svn-src-head@freebsd.org Wed Feb 26 11:29:04 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id BDBD8254C88; Wed, 26 Feb 2020 11:29:04 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 48SD8c47tbz4LLN; Wed, 26 Feb 2020 11:29:04 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 60C6626921; Wed, 26 Feb 2020 11:29:04 +0000 (UTC) (envelope-from andrew@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 01QBT4jQ079533; Wed, 26 Feb 2020 11:29:04 GMT (envelope-from andrew@FreeBSD.org) Received: (from andrew@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 01QBT3cU079532; Wed, 26 Feb 2020 11:29:03 GMT (envelope-from andrew@FreeBSD.org) Message-Id: <202002261129.01QBT3cU079532@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: andrew set sender to andrew@FreeBSD.org using -f From: Andrew Turner Date: Wed, 26 Feb 2020 11:29:03 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r358326 - in head/sys/arm64: arm64 include X-SVN-Group: head X-SVN-Commit-Author: andrew X-SVN-Commit-Paths: in head/sys/arm64: arm64 include X-SVN-Commit-Revision: 358326 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 26 Feb 2020 11:29:04 -0000 Author: andrew Date: Wed Feb 26 11:29:03 2020 New Revision: 358326 URL: https://svnweb.freebsd.org/changeset/base/358326 Log: Add more arm64 CTR_EL0 register fields While here make the _SIZE macros return the size in bytes, not the log2 of the size Sponsored by: Innovate UK Modified: head/sys/arm64/arm64/machdep.c head/sys/arm64/include/armreg.h Modified: head/sys/arm64/arm64/machdep.c ============================================================================== --- head/sys/arm64/arm64/machdep.c Wed Feb 26 08:47:18 2020 (r358325) +++ head/sys/arm64/arm64/machdep.c Wed Feb 26 11:29:03 2020 (r358326) @@ -1047,20 +1047,16 @@ bus_probe(void) static void cache_setup(void) { - int dcache_line_shift, icache_line_shift, dczva_line_shift; + int dczva_line_shift; uint32_t ctr_el0; uint32_t dczid_el0; ctr_el0 = READ_SPECIALREG(ctr_el0); - /* Read the log2 words in each D cache line */ - dcache_line_shift = CTR_DLINE_SIZE(ctr_el0); /* Get the D cache line size */ - dcache_line_size = sizeof(int) << dcache_line_shift; - + dcache_line_size = CTR_DLINE_SIZE(ctr_el0); /* And the same for the I cache */ - icache_line_shift = CTR_ILINE_SIZE(ctr_el0); - icache_line_size = sizeof(int) << icache_line_shift; + icache_line_size = CTR_ILINE_SIZE(ctr_el0); idcache_line_size = MIN(dcache_line_size, icache_line_size); Modified: head/sys/arm64/include/armreg.h ============================================================================== --- head/sys/arm64/include/armreg.h Wed Feb 26 08:47:18 2020 (r358325) +++ head/sys/arm64/include/armreg.h Wed Feb 26 11:29:03 2020 (r358326) @@ -82,12 +82,39 @@ #define CPACR_TTA (0x1 << 28) /* CTR_EL0 - Cache Type Register */ +#define CTR_RES1 (1 << 31) +#define CTR_TminLine_SHIFT 32 +#define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT) +#define CTR_TminLine_VAL(reg) ((reg) & CTR_TminLine_MASK) +#define CTR_DIC_SHIFT 29 +#define CTR_DIC_MASK (0x1 << CTR_DIC_SHIFT) +#define CTR_DIC_VAL(reg) ((reg) & CTR_DIC_MASK) +#define CTR_IDC_SHIFT 28 +#define CTR_IDC_MASK (0x1 << CTR_IDC_SHIFT) +#define CTR_IDC_VAL(reg) ((reg) & CTR_IDC_MASK) +#define CTR_CWG_SHIFT 24 +#define CTR_CWG_MASK (0xf << CTR_CWG_SHIFT) +#define CTR_CWG_VAL(reg) ((reg) & CTR_CWG_MASK) +#define CTR_CWG_SIZE(reg) (4 << (CTR_CWG_VAL(reg) >> CTR_CWG_SHIFT)) +#define CTR_ERG_SHIFT 20 +#define CTR_ERG_MASK (0xf << CTR_ERG_SHIFT) +#define CTR_ERG_VAL(reg) ((reg) & CTR_ERG_MASK) +#define CTR_ERG_SIZE(reg) (4 << (CTR_ERG_VAL(reg) >> CTR_ERG_SHIFT)) #define CTR_DLINE_SHIFT 16 #define CTR_DLINE_MASK (0xf << CTR_DLINE_SHIFT) -#define CTR_DLINE_SIZE(reg) (((reg) & CTR_DLINE_MASK) >> CTR_DLINE_SHIFT) +#define CTR_DLINE_VAL(reg) ((reg) & CTR_DLINE_MASK) +#define CTR_DLINE_SIZE(reg) (4 << (CTR_DLINE_VAL(reg) >> CTR_DLINE_SHIFT)) +#define CTR_L1IP_SHIFT 14 +#define CTR_L1IP_MASK (0x3 << CTR_L1IP_SHIFT) +#define CTR_L1IP_VAL(reg) ((reg) & CTR_L1IP_MASK) +#define CTR_L1IP_VPIPT (0 << CTR_L1IP_SHIFT) +#define CTR_L1IP_AIVIVT (1 << CTR_L1IP_SHIFT) +#define CTR_L1IP_VIVT (2 << CTR_L1IP_SHIFT) +#define CTR_L1IP_PIPT (3 << CTR_L1IP_SHIFT) #define CTR_ILINE_SHIFT 0 #define CTR_ILINE_MASK (0xf << CTR_ILINE_SHIFT) -#define CTR_ILINE_SIZE(reg) (((reg) & CTR_ILINE_MASK) >> CTR_ILINE_SHIFT) +#define CTR_ILINE_VAL(reg) ((reg) & CTR_ILINE_MASK) +#define CTR_ILINE_SIZE(reg) (4 << (CTR_ILINE_VAL(reg) >> CTR_ILINE_SHIFT)) /* DAIF - Interrupt Mask Bits */ #define DAIF_D_MASKED (1 << 9)