Date: Mon, 9 Jul 2012 10:17:06 +0000 (UTC) From: "Jayachandran C." <jchandra@FreeBSD.org> To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r238289 - head/sys/mips/nlm Message-ID: <201207091017.q69AH61P010030@svn.freebsd.org>
next in thread | raw e-mail | index | archive | help
Author: jchandra Date: Mon Jul 9 10:17:06 2012 New Revision: 238289 URL: http://svn.freebsd.org/changeset/base/238289 Log: Fix PCIe hardware swap configuration for Netlogic XLP The last 12 bits of the limit registers have to be set to 1. These bits are not significant in bridge BARs and are 0 on read, but the bits are valid in the swap limit register and needs to be set. Modified: head/sys/mips/nlm/xlp_pci.c Modified: head/sys/mips/nlm/xlp_pci.c ============================================================================== --- head/sys/mips/nlm/xlp_pci.c Mon Jul 9 09:38:53 2012 (r238288) +++ head/sys/mips/nlm/xlp_pci.c Mon Jul 9 10:17:06 2012 (r238289) @@ -507,13 +507,13 @@ xlp_pcib_hardware_swap_enable(int node, nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_BASE, bar); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEMEM_LIMIT0 + link); - nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar); + nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_MEM_LIM, bar | 0xFFF); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_BASE0 + link); nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_BASE, bar); bar = nlm_read_bridge_reg(bbase, BRIDGE_PCIEIO_LIMIT0 + link); - nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar); + nlm_write_pci_reg(linkpcibase, PCIE_BYTE_SWAP_IO_LIM, bar | 0xFFF); } static int
Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201207091017.q69AH61P010030>