From owner-svn-src-stable@freebsd.org Wed Mar 4 21:01:25 2020 Return-Path: Delivered-To: svn-src-stable@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id E969A2510CA; Wed, 4 Mar 2020 21:01:25 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 48XmWn460sz3PpD; Wed, 4 Mar 2020 21:01:25 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 6F50C241ED; Wed, 4 Mar 2020 21:01:25 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 024L1PTD019850; Wed, 4 Mar 2020 21:01:25 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 024L1PSW019848; Wed, 4 Mar 2020 21:01:25 GMT (envelope-from manu@FreeBSD.org) Message-Id: <202003042101.024L1PSW019848@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Wed, 4 Mar 2020 21:01:25 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r358644 - in stable/12/sys: arm64/rockchip/clk conf dev/extres/clk X-SVN-Group: stable-12 X-SVN-Commit-Author: manu X-SVN-Commit-Paths: in stable/12/sys: arm64/rockchip/clk conf dev/extres/clk X-SVN-Commit-Revision: 358644 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Mar 2020 21:01:26 -0000 Author: manu Date: Wed Mar 4 21:01:25 2020 New Revision: 358644 URL: https://svnweb.freebsd.org/changeset/base/358644 Log: MFC r354554-r354558, r355115 r354554 by mmel: Implement support for (soft)linked clocks. This kind of clock nodes represent temporary placeholder for clocks defined later in boot process. Also, these are necessary to break circular dependencies occasionally occurring in complex clock graphs. r354555 by mmel: Cleanup Rockchip clocks implementation. - style - unify dprinf defines - make dprinf's 32-bit compatible Not a functional change. Reviewed by: manu, imp Differential Revision: https://reviews.freebsd.org/D22281 r354556 by mmel: Enhance Rockchip clocks implementation. - add support for fractional dividers - allow to declare fixed and linked clock Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D22282 r354557 by mmel: Tidy up Rockchip composite clock. - add support for log2 based dividers - use proper write mask when writing to divider register Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D22283 r354558 by mmel: Remove explicit declaration of rk_clk_fract_set_freq() function forgotten in r354556. MFC with: r354556 Noticed by: manu r355115 by mmel: Finish implementation of RK3299 clocks. - implement of all but mmc clocks. MMC clocks will be added later by own commit. - use 'link' clock type for external clocks. - use macros for initialization of structure's named members. Reviewed by: manu Differential Revision: https://reviews.freebsd.org/D22441 Added: stable/12/sys/arm64/rockchip/clk/rk3399_cru_dt.h - copied unchanged from r355115, head/sys/arm64/rockchip/clk/rk3399_cru_dt.h stable/12/sys/arm64/rockchip/clk/rk_clk_fract.c - copied unchanged from r354558, head/sys/arm64/rockchip/clk/rk_clk_fract.c stable/12/sys/arm64/rockchip/clk/rk_clk_fract.h - copied unchanged from r354558, head/sys/arm64/rockchip/clk/rk_clk_fract.h stable/12/sys/dev/extres/clk/clk_link.c - copied unchanged from r354558, head/sys/dev/extres/clk/clk_link.c stable/12/sys/dev/extres/clk/clk_link.h - copied unchanged from r354558, head/sys/dev/extres/clk/clk_link.h Modified: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c stable/12/sys/arm64/rockchip/clk/rk_clk_armclk.c stable/12/sys/arm64/rockchip/clk/rk_clk_composite.c stable/12/sys/arm64/rockchip/clk/rk_clk_composite.h stable/12/sys/arm64/rockchip/clk/rk_clk_gate.c stable/12/sys/arm64/rockchip/clk/rk_clk_mux.c stable/12/sys/arm64/rockchip/clk/rk_clk_pll.c stable/12/sys/arm64/rockchip/clk/rk_cru.c stable/12/sys/arm64/rockchip/clk/rk_cru.h stable/12/sys/conf/files stable/12/sys/conf/files.arm64 stable/12/sys/dev/extres/clk/clk.c stable/12/sys/dev/extres/clk/clk.h Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/rockchip/clk/rk3399_cru.c ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3399_cru.c Wed Mar 4 21:01:22 2020 (r358643) +++ stable/12/sys/arm64/rockchip/clk/rk3399_cru.c Wed Mar 4 21:01:25 2020 (r358644) @@ -50,1930 +50,1188 @@ __FBSDID("$FreeBSD$"); #include -/* GATES */ +#include -#define SCLK_USB2PHY0_REF 123 -#define SCLK_USB2PHY1_REF 124 -#define SCLK_USB3OTG0_REF 129 -#define SCLK_USB3OTG1_REF 130 -#define SCLK_USB3OTG0_SUSPEND 131 -#define SCLK_USB3OTG1_SUSPEND 132 -#define ACLK_EMMC_CORE 241 -#define ACLK_EMMC_NOC 242 -#define ACLK_EMMC_GRF 243 -#define ACLK_USB3_NOC 245 -#define ACLK_USB3OTG0 246 -#define ACLK_USB3OTG1 247 -#define ACLK_USB3_RKSOC_AXI_PERF 248 -#define ACLK_USB3_GRF 249 -#define PCLK_GPIO2 336 -#define PCLK_GPIO3 337 -#define PCLK_GPIO4 338 -#define PCLK_I2C1 341 -#define PCLK_I2C2 342 -#define PCLK_I2C3 343 -#define PCLK_I2C5 344 -#define PCLK_I2C6 345 -#define PCLK_I2C7 346 -#define PCLK_SPI0 347 -#define PCLK_SPI1 348 -#define PCLK_SPI2 349 -#define PCLK_SPI4 350 -#define PCLK_SPI5 351 -#define HCLK_HOST0 456 -#define HCLK_HOST0_ARB 457 -#define HCLK_HOST1 458 -#define HCLK_HOST1_ARB 459 -#define HCLK_SDMMC 462 +#define CRU_CLKSEL_CON(x) (0x100 + (x) * 0x4) +#define CRU_CLKGATE_CON(x) (0x300 + (x) * 0x4) + +/* GATES */ + static struct rk_cru_gate rk3399_gates[] = { /* CRU_CLKGATE_CON0 */ - CRU_GATE(0, "clk_core_l_lpll_src", "lpll", 0x300, 0) - CRU_GATE(0, "clk_core_l_bpll_src", "bpll", 0x300, 1) - CRU_GATE(0, "clk_core_l_dpll_src", "dpll", 0x300, 2) - CRU_GATE(0, "clk_core_l_gpll_src", "gpll", 0x300, 3) + /* 15-8 unused */ + GATE(SCLK_PVTM_CORE_L, "clk_pvtm_core_l", "xin24m", 0, 7), + GATE(0, "pclk_dbg_core_l", "pclk_dbg_core_l_c", 0, 6), + GATE(0, "atclk_core_l", "atclk_core_l_c", 0, 5), + GATE(0, "aclkm_core_l", "aclkm_core_l_c", 0, 4), + GATE(0, "clk_core_l_gpll_src", "gpll", 0, 3), + GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2), + GATE(0, "clk_core_l_bpll_src", "bpll", 0, 1), + GATE(0, "clk_core_l_lpll_src", "lpll", 0, 0), /* CRU_CLKGATE_CON1 */ - CRU_GATE(0, "clk_core_b_lpll_src", "lpll", 0x304, 0) - CRU_GATE(0, "clk_core_b_bpll_src", "bpll", 0x304, 1) - CRU_GATE(0, "clk_core_b_dpll_src", "dpll", 0x304, 2) - CRU_GATE(0, "clk_core_b_gpll_src", "gpll", 0x304, 3) + /* 15 - 8 unused */ + GATE(SCLK_PVTM_CORE_B, "clk_pvtm_core_b", "xin24m", 1, 7), + GATE(0, "pclk_dbg_core_b","pclk_dbg_core_b_c", 1, 6), + GATE(0, "atclk_core_b", "atclk_core_b_c", 1, 5), + GATE(0, "aclkm_core_b", "aclkm_core_b_c", 1, 4), + GATE(0, "clk_core_b_gpll_src", "gpll", 1, 3), + GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2), + GATE(0, "clk_core_b_bpll_src", "bpll", 1, 1), + GATE(0, "clk_core_b_lpll_src", "lpll", 1, 0), + /* CRU_CLKGATE_CON2 */ + /* 15 - 11 unused */ + GATE(0, "npll_cs", "npll", 2, 10), + GATE(0, "gpll_cs", "gpll", 2, 9), + GATE(0, "cpll_cs", "cpll", 2, 8), + GATE(SCLK_CCI_TRACE, "clk_cci_trace", "clk_cci_trace_c", 2, 7), + GATE(0, "gpll_cci_trace", "gpll", 2, 6), + GATE(0, "cpll_cci_trace", "cpll", 2, 5), + GATE(0, "aclk_cci_pre", "aclk_cci_pre_c", 2, 4), + GATE(0, "vpll_aclk_cci_src", "vpll", 2, 3), + GATE(0, "npll_aclk_cci_src", "npll", 2, 2), + GATE(0, "gpll_aclk_cci_src", "gpll", 2, 1), + GATE(0, "cpll_aclk_cci_src", "cpll", 2, 0), + + /* CRU_CLKGATE_CON3 */ + /* 15 - 8 unused */ + GATE(0, "aclk_center", "aclk_center_c", 3, 7), + /* 6 unused */ + /* 5 unused */ + GATE(PCLK_DDR, "pclk_ddr", "pclk_ddr_c", 3, 4), + GATE(0, "clk_ddrc_gpll_src", "gpll", 3, 3), + GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2), + GATE(0, "clk_ddrc_bpll_src", "bpll", 3, 1), + GATE(0, "clk_ddrc_lpll_src", "lpll", 3, 0), + + + /* CRU_CLKGATE_CON4 */ + /* 15 - 12 unused */ + GATE(SCLK_PVTM_DDR, "clk_pvtm_ddr", "xin24m", 4, 11), + GATE(0, "clk_rga_core", "clk_rga_core_c", 4, 10), + GATE(0, "hclk_rga_pre", "hclk_rga_pre_c", 4, 9), + GATE(0, "aclk_rga_pre", "aclk_rga_pre_c", 4, 8), + GATE(0, "hclk_iep_pre", "hclk_iep_pre_c", 4, 7), + GATE(0, "aclk_iep_pre", "aclk_iep_pre_c", 4, 6), + GATE(SCLK_VDU_CA, "clk_vdu_ca", "clk_vdu_ca_c", 4, 5), + GATE(SCLK_VDU_CORE, "clk_vdu_core", "clk_vdu_core_c", 4, 4), + GATE(0, "hclk_vdu_pre", "hclk_vdu_pre_c", 4, 3), + GATE(0, "aclk_vdu_pre", "aclk_vdu_pre_c", 4, 2), + GATE(0, "hclk_vcodec_pre", "hclk_vcodec_pre_c", 4, 1), + GATE(0, "aclk_vcodec_pre", "aclk_vcodec_pre_c", 4, 0), + /* CRU_CLKGATE_CON5 */ - CRU_GATE(0, "cpll_aclk_perihp_src", "cpll", 0x314, 0) - CRU_GATE(0, "gpll_aclk_perihp_src", "gpll", 0x314, 1) + /* 15 - 10 unused */ + GATE(SCLK_MAC_TX, "clk_rmii_tx", "clk_rmii_src", 5, 9), + GATE(SCLK_MAC_RX, "clk_rmii_rx", "clk_rmii_src", 5, 8), + GATE(SCLK_MACREF, "clk_mac_ref", "clk_rmii_src", 5, 7), + GATE(SCLK_MACREF_OUT, "clk_mac_refout", "clk_rmii_src", 5, 6), + GATE(SCLK_MAC, "clk_gmac", "clk_gmac_c", 5, 5), + GATE(PCLK_PERIHP, "pclk_perihp", "pclk_perihp_c", 5, 4), + GATE(HCLK_PERIHP, "hclk_perihp", "hclk_perihp_c", 5, 3), + GATE(ACLK_PERIHP, "aclk_perihp", "aclk_perihp_c", 5, 2), + GATE(0, "cpll_aclk_perihp_src", "cpll", 5, 1), + GATE(0, "gpll_aclk_perihp_src", "gpll", 5, 0), /* CRU_CLKGATE_CON6 */ - CRU_GATE(0, "gpll_aclk_emmc_src", "gpll", 0x318, 12) - CRU_GATE(0, "cpll_aclk_emmc_src", "cpll", 0x318, 13) - CRU_GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 0x318, 5) - CRU_GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 0x318, 6) + /* 15 unused */ + GATE(SCLK_EMMC, "clk_emmc", "clk_emmc_c", 6, 14), + GATE(0, "cpll_aclk_emmc_src", "cpll", 6, 13), + GATE(0, "gpll_aclk_emmc_src", "gpll", 6, 12), + GATE(0, "pclk_gmac_pre", "pclk_gmac_pre_c", 6, 11), + GATE(0, "aclk_gmac_pre", "aclk_gmac_pre_c", 6, 10), + GATE(0, "cpll_aclk_gmac_src", "cpll", 6, 9), + GATE(0, "gpll_aclk_gmac_src", "gpll", 6, 8), + /* 7 unused */ + GATE(SCLK_USB2PHY1_REF, "clk_usb2phy1_ref", "xin24m", 6, 6), + GATE(SCLK_USB2PHY0_REF, "clk_usb2phy0_ref", "xin24m", 6, 5), + GATE(SCLK_HSICPHY, "clk_hsicphy", "clk_hsicphy_c", 6, 4), + GATE(0, "clk_pcie_core_cru", "clk_pcie_core_cru_c", 6, 3), + GATE(SCLK_PCIE_PM, "clk_pcie_pm", "clk_pcie_pm_c", 6, 2), + GATE(SCLK_SDMMC, "clk_sdmmc", "clk_sdmmc_c", 6, 1), + GATE(SCLK_SDIO, "clk_sdio", "clk_sdio_c", 6, 0), /* CRU_CLKGATE_CON7 */ - CRU_GATE(0, "gpll_aclk_perilp0_src", "gpll", 0x31C, 0) - CRU_GATE(0, "cpll_aclk_perilp0_src", "cpll", 0x31C, 1) + /* 15 - 10 unused */ + GATE(FCLK_CM0S, "fclk_cm0s", "fclk_cm0s_c", 7, 9), + GATE(SCLK_CRYPTO1, "clk_crypto1", "clk_crypto1_c", 7, 8), + GATE(SCLK_CRYPTO0, "clk_crypto0", "clk_crypto0_c", 7, 7), + GATE(0, "cpll_fclk_cm0s_src", "cpll", 7, 6), + GATE(0, "gpll_fclk_cm0s_src", "gpll", 7, 5), + GATE(PCLK_PERILP0, "pclk_perilp0", "pclk_perilp0_c", 7, 4), + GATE(HCLK_PERILP0, "hclk_perilp0", "hclk_perilp0_c", 7, 3), + GATE(ACLK_PERILP0, "aclk_perilp0", "aclk_perilp0_c", 7, 2), + GATE(0, "cpll_aclk_perilp0_src", "cpll", 7, 1), + GATE(0, "gpll_aclk_perilp0_src", "gpll", 7, 0), /* CRU_CLKGATE_CON8 */ - CRU_GATE(0, "hclk_perilp1_cpll_src", "cpll", 0x320, 1) - CRU_GATE(0, "hclk_perilp1_gpll_src", "gpll", 0x320, 0) + GATE(SCLK_SPDIF_8CH, "clk_spdif", "clk_spdif_mux", 8, 15), + GATE(0, "clk_spdif_frac", "clk_spdif_frac_c", 8, 14), + GATE(0, "clk_spdif_div", "clk_spdif_div_c", 8, 13), + GATE(SCLK_I2S_8CH_OUT, "clk_i2sout", "clk_i2sout_c", 8, 12), + GATE(SCLK_I2S2_8CH, "clk_i2s2", "clk_i2s2_mux", 8, 11), + GATE(0, "clk_i2s2_frac", "clk_i2s2_frac_c", 8, 10), + GATE(0, "clk_i2s2_div", "clk_i2s2_div_c", 8, 9), + GATE(SCLK_I2S1_8CH, "clk_i2s1", "clk_i2s1_mux", 8, 8), + GATE(0, "clk_i2s1_frac", "clk_i2s1_frac_c", 8, 7), + GATE(0, "clk_i2s1_div", "clk_i2s1_div_c", 8, 6), + GATE(SCLK_I2S0_8CH, "clk_i2s0", "clk_i2s0_mux", 8, 5), + GATE(0, "clk_i2s0_frac","clk_i2s0_frac_c", 8, 4), + GATE(0, "clk_i2s0_div","clk_i2s0_div_c", 8, 3), + GATE(PCLK_PERILP1, "pclk_perilp1", "pclk_perilp1_c", 8, 2), + GATE(HCLK_PERILP1, "cpll_hclk_perilp1_src", "cpll", 8, 1), + GATE(0, "gpll_hclk_perilp1_src", "gpll", 8, 0), - /* CRU_CLKGATE_CON12 */ - CRU_GATE(SCLK_USB3OTG0_REF, "sclk_usb3otg0_ref", "xin24m", 0x330, 1) - CRU_GATE(SCLK_USB3OTG1_REF, "sclk_usb3otg1_ref", "xin24m", 0x330, 2) - CRU_GATE(SCLK_USB3OTG0_SUSPEND, "sclk_usb3otg0_suspend", "xin24m", 0x330, 3) - CRU_GATE(SCLK_USB3OTG1_SUSPEND, "sclk_usb3otg1_suspend", "xin24m", 0x330, 4) + /* CRU_CLKGATE_CON9 */ + GATE(SCLK_SPI4, "clk_spi4", "clk_spi4_c", 9, 15), + GATE(SCLK_SPI2, "clk_spi2", "clk_spi2_c", 9, 14), + GATE(SCLK_SPI1, "clk_spi1", "clk_spi1_c", 9, 13), + GATE(SCLK_SPI0, "clk_spi0", "clk_spi0_c", 9, 12), + GATE(SCLK_SARADC, "clk_saradc", "clk_saradc_c", 9, 11), + GATE(SCLK_TSADC, "clk_tsadc", "clk_tsadc_c", 9, 10), + /* 9 - 8 unused */ + GATE(0, "clk_uart3_frac", "clk_uart3_frac_c", 9, 7), + GATE(0, "clk_uart3_div", "clk_uart3_div_c", 9, 6), + GATE(0, "clk_uart2_frac", "clk_uart2_frac_c", 9, 5), + GATE(0, "clk_uart2_div", "clk_uart2_div_c", 9, 4), + GATE(0, "clk_uart1_frac", "clk_uart1_frac_c", 9, 3), + GATE(0, "clk_uart1_div", "clk_uart1_div_c", 9, 2), + GATE(0, "clk_uart0_frac", "clk_uart0_frac_c", 9, 1), + GATE(0, "clk_uart0_div", "clk_uart0_div_c", 9, 0), - /* CRU_CLKGATE_CON20 */ - CRU_GATE(HCLK_HOST0, "hclk_host0", "hclk_perihp", 0x350, 5) - CRU_GATE(HCLK_HOST0_ARB, "hclk_host0_arb", "hclk_perihp", 0x350, 6) - CRU_GATE(HCLK_HOST1, "hclk_host1", "hclk_perihp", 0x350, 7) - CRU_GATE(HCLK_HOST1_ARB, "hclk_host1_arb", "hclk_perihp", 0x350, 8) + /* CRU_CLKGATE_CON10 */ + GATE(SCLK_VOP1_PWM, "clk_vop1_pwm", "clk_vop1_pwm_c", 10, 15), + GATE(SCLK_VOP0_PWM, "clk_vop0_pwm", "clk_vop0_pwm_c", 10, 14), + GATE(DCLK_VOP0_DIV, "dclk_vop0_div", "dclk_vop0_div_c", 10, 12), + GATE(DCLK_VOP1_DIV, "dclk_vop1_div", "dclk_vop1_div_c", 10, 13), + GATE(0, "hclk_vop1_pre", "hclk_vop1_pre_c", 10, 11), + GATE(ACLK_VOP1_PRE, "aclk_vop1_pre", "aclk_vop1_pre_c", 10, 10), + GATE(0, "hclk_vop0_pre", "hclk_vop0_pre_c", 10, 9), + GATE(ACLK_VOP0_PRE, "aclk_vop0_pre", "aclk_vop0_pre_c", 10, 8), + GATE(0, "clk_cifout_src", "clk_cifout_src_c", 10, 7), + GATE(SCLK_SPDIF_REC_DPTX, "clk_spdif_rec_dptx", "clk_spdif_rec_dptx_c", 10, 6), + GATE(SCLK_I2C7, "clk_i2c7", "clk_i2c7_c", 10, 5), + GATE(SCLK_I2C3, "clk_i2c3", "clk_i2c3_c", 10, 4), + GATE(SCLK_I2C6, "clk_i2c6", "clk_i2c6_c", 10, 3), + GATE(SCLK_I2C2, "clk_i2c2", "clk_i2c2_c", 10, 2), + GATE(SCLK_I2C5, "clk_i2c5", "clk_i2c5_c", 10, 1), + GATE(SCLK_I2C1, "clk_i2c1", "clk_i2c1_c", 10, 0), - /* CRU_CLKGATE_CON22 */ - CRU_GATE(PCLK_I2C7, "pclk_rki2c7", "pclk_perilp1", 0x358, 5) - CRU_GATE(PCLK_I2C1, "pclk_rki2c1", "pclk_perilp1", 0x358, 6) - CRU_GATE(PCLK_I2C5, "pclk_rki2c5", "pclk_perilp1", 0x358, 7) - CRU_GATE(PCLK_I2C6, "pclk_rki2c6", "pclk_perilp1", 0x358, 8) - CRU_GATE(PCLK_I2C2, "pclk_rki2c2", "pclk_perilp1", 0x358, 9) - CRU_GATE(PCLK_I2C3, "pclk_rki2c3", "pclk_perilp1", 0x358, 10) - /* CRU_CLKGATE_CON23 */ - CRU_GATE(PCLK_SPI0, "pclk_spi0", "pclk_perilp1", 0x35C, 10) - CRU_GATE(PCLK_SPI1, "pclk_spi1", "pclk_perilp1", 0x35C, 11) - CRU_GATE(PCLK_SPI2, "pclk_spi2", "pclk_perilp1", 0x35C, 12) - CRU_GATE(PCLK_SPI4, "pclk_spi4", "pclk_perilp1", 0x35C, 13) + /* CRU_CLKGATE_CON11 */ + GATE(SCLK_MIPIDPHY_CFG, "clk_mipidphy_cfg", "xin24m", 11, 15), + GATE(SCLK_MIPIDPHY_REF, "clk_mipidphy_ref", "xin24m", 11, 14), + /* 13-12 unused */ + GATE(PCLK_EDP, "pclk_edp", "pclk_edp_c", 11, 11), + GATE(PCLK_HDCP, "pclk_hdcp", "pclk_hdcp_c", 11, 10), + /* 9 unuwsed */ + GATE(SCLK_DP_CORE, "clk_dp_core", "clk_dp_core_c", 11, 8), + GATE(SCLK_HDMI_CEC, "clk_hdmi_cec", "clk_hdmi_cec_c", 11, 7), + GATE(SCLK_HDMI_SFR, "clk_hdmi_sfr", "xin24m", 11, 6), + GATE(SCLK_ISP1, "clk_isp1", "clk_isp1_c", 11, 5), + GATE(SCLK_ISP0, "clk_isp0", "clk_isp0_c", 11, 4), + GATE(HCLK_HDCP, "hclk_hdcp", "hclk_hdcp_c", 11, 3), + GATE(ACLK_HDCP, "aclk_hdcp", "aclk_hdcp_c", 11, 2), + GATE(PCLK_VIO, "pclk_vio", "pclk_vio_c", 11, 1), + GATE(ACLK_VIO, "aclk_vio", "aclk_vio_c", 11, 0), - /* CRU_CLKGATE_CON30 */ - CRU_GATE(ACLK_USB3_NOC, "aclk_usb3_noc", "aclk_usb3", 0x378, 0) - CRU_GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb3", 0x378, 1) - CRU_GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb3", 0x378, 2) - CRU_GATE(ACLK_USB3_RKSOC_AXI_PERF, "aclk_usb3_rksoc_axi_perf", "aclk_usb3", 0x378, 3) - CRU_GATE(ACLK_USB3_GRF, "aclk_usb3_grf", "aclk_usb3", 0x378, 4) + /* CRU_CLKGATE_CON12 */ + /* 15 - 14 unused */ + GATE(HCLK_SD, "hclk_sd", "hclk_sd_c", 12, 13), + GATE(ACLK_GIC_PRE, "aclk_gic_pre", "aclk_gic_pre_c", 12, 12), + GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_c", 12, 11), + GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_c", 12, 10), + GATE(HCLK_ISP0, "hclk_isp0", "hclk_isp0_c", 12, 9), + GATE(ACLK_ISP0, "aclk_isp0", "aclk_isp0_c", 12, 8), + /* 7 unused */ + GATE(SCLK_PCIEPHY_REF100M, "clk_pciephy_ref100m", "clk_pciephy_ref100m_c", 12, 6), + /* 5 unused */ + GATE(SCLK_USB3OTG1_SUSPEND, "clk_usb3otg1_suspend", "clk_usb3otg1_suspend_c", 12, 4), + GATE(SCLK_USB3OTG0_SUSPEND, "clk_usb3otg0_suspend", "clk_usb3otg0_suspend_c", 12, 3), + GATE(SCLK_USB3OTG1_REF, "clk_usb3otg1_ref", "xin24m", 12, 2), + GATE(SCLK_USB3OTG0_REF, "clk_usb3otg0_ref", "xin24m", 12, 1), + GATE(ACLK_USB3, "aclk_usb3", "aclk_usb3_c", 12, 0), - /* CRU_CLKGATE_CON31 */ - CRU_GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_alive", 0x37c, 3) - CRU_GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_alive", 0x37c, 4) - CRU_GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_alive", 0x37c, 5) + /* CRU_CLKGATE_CON13 */ + GATE(SCLK_TESTCLKOUT2, "clk_testout2", "clk_testout2_c", 13, 15), + GATE(SCLK_TESTCLKOUT1, "clk_testout1", "clk_testout1_c", 13, 14), + GATE(SCLK_SPI5, "clk_spi5", "clk_spi5_c", 13, 13), + GATE(0, "clk_usbphy0_480m_src", "clk_usbphy0_480m", 13, 12), + GATE(0, "clk_usbphy1_480m_src", "clk_usbphy1_480m", 13, 12), + GATE(0, "clk_test", "clk_test_c", 13, 11), + /* 10 unused */ + GATE(0, "clk_test_frac", "clk_test_frac_c", 13, 9), + /* 8 unused */ + GATE(SCLK_UPHY1_TCPDCORE, "clk_uphy1_tcpdcore", "clk_uphy1_tcpdcore_c", 13, 7), + GATE(SCLK_UPHY1_TCPDPHY_REF, "clk_uphy1_tcpdphy_ref", "clk_uphy1_tcpdphy_ref_c", 13, 6), + GATE(SCLK_UPHY0_TCPDCORE, "clk_uphy0_tcpdcore", "clk_uphy0_tcpdcore_c", 13, 5), + GATE(SCLK_UPHY0_TCPDPHY_REF, "clk_uphy0_tcpdphy_ref", "clk_uphy0_tcpdphy_ref_c", 13, 4), + /* 3 - 2 unused */ + GATE(SCLK_PVTM_GPU, "aclk_pvtm_gpu", "xin24m", 13, 1), + GATE(0, "aclk_gpu_pre", "aclk_gpu_pre_c", 13, 0), - /* CRU_CLKGATE_CON32 */ - CRU_GATE(ACLK_EMMC_CORE, "aclk_emmccore", "aclk_emmc", 0x380, 8) - CRU_GATE(ACLK_EMMC_NOC, "aclk_emmc_noc", "aclk_emmc", 0x380, 9) - CRU_GATE(ACLK_EMMC_GRF, "aclk_emmcgrf", "aclk_emmc", 0x380, 10) + /* CRU_CLKGATE_CON14 */ + /* 15 - 14 unused */ + GATE(ACLK_PERF_CORE_L, "aclk_perf_core_l", "aclkm_core_l", 14, 13), + GATE(ACLK_CORE_ADB400_CORE_L_2_CCI500, "aclk_core_adb400_core_l_2_cci500", "aclkm_core_l", 14, 12), + GATE(ACLK_GIC_ADB400_CORE_L_2_GIC, "aclk_core_adb400_core_l_2_gic", "armclkl", 14, 11), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_L, "aclk_core_adb400_gic_2_core_l", "armclkl", 14, 10), + GATE(0, "clk_dbg_pd_core_l", "armclkl", 14, 9), + /* 8 - 7 unused */ + GATE(ACLK_PERF_CORE_B, "aclk_perf_core_b", "aclkm_core_b", 14, 6), + GATE(ACLK_CORE_ADB400_CORE_B_2_CCI500, "aclk_core_adb400_core_b_2_cci500", "aclkm_core_b", 14, 5), + GATE(ACLK_GIC_ADB400_CORE_B_2_GIC, "aclk_core_adb400_core_b_2_gic", "armclkb", 14, 4), + GATE(ACLK_GIC_ADB400_GIC_2_CORE_B, "aclk_core_adb400_gic_2_core_b", "armclkb", 14, 3), + GATE(0, "pclk_dbg_cxcs_pd_core_b", "pclk_dbg_core_b", 14, 2), + GATE(0, "clk_dbg_pd_core_b", "armclkb", 14, 1), + /* 0 unused */ - /* CRU_CLKGATE_CON33 */ - CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_sd", 0x384, 8) + /* CRU_CLKGATE_CON15 */ + /* 15 - 8 unused */ + GATE(ACLK_CCI_GRF, "aclk_cci_grf", "aclk_cci_pre", 15, 7), + GATE(0, "clk_dbg_noc", "clk_cs", 15, 6), + GATE(0, "clk_dbg_cxcs", "clk_cs", 15, 5), + GATE(ACLK_CCI_NOC1, "aclk_cci_noc1", "aclk_cci_pre", 15, 4), + GATE(ACLK_CCI_NOC0, "aclk_cci_noc0", "aclk_cci_pre", 15, 3), + GATE(ACLK_CCI, "aclk_cci", "aclk_cci_pre", 15, 2), + GATE(ACLK_ADB400M_PD_CORE_B, "aclk_adb400m_pd_core_b", "aclk_cci_pre", 15, 1), + GATE(ACLK_ADB400M_PD_CORE_L, "aclk_adb400m_pd_core_l", "aclk_cci_pre", 15, 0), - /* CRU_CLKGATE_CON34 */ - CRU_GATE(PCLK_SPI4, "pclk_spi5", "pclk_perilp1", 0x388, 5) -}; + /* CRU_CLKGATE_CON16 */ + /* 15 - 12 unused */ + GATE(HCLK_RGA_NOC, "hclk_rga_noc", "hclk_rga_pre", 16, 11), + GATE(HCLK_RGA, "hclk_rga", "hclk_rga_pre", 16, 10), + GATE(ACLK_RGA_NOC, "aclk_rga_noc", "aclk_rga_pre", 16, 9), + GATE(ACLK_RGA, "aclk_rga", "aclk_rga_pre", 16, 8), + /* 7 - 4 unused */ + GATE(HCLK_IEP_NOC, "hclk_iep_noc", "hclk_iep_pre", 16, 3), + GATE(HCLK_IEP, "hclk_iep", "hclk_iep_pre", 16, 2), + GATE(ACLK_IEP_NOC, "aclk_iep_noc", "aclk_iep_pre", 16, 1), + GATE(ACLK_IEP, "aclk_iep", "aclk_iep_pre", 16, 0), -/* - * PLLs - */ + /* CRU_CLKGATE_CON17 */ + /* 15 - 12 unused */ + GATE(HCLK_VDU_NOC, "hclk_vdu_noc", "hclk_vdu_pre", 17, 11), + GATE(HCLK_VDU, "hclk_vdu", "hclk_vdu_pre", 17, 10), + GATE(ACLK_VDU_NOC, "aclk_vdu_noc", "aclk_vdu_pre", 17, 9), + GATE(ACLK_VDU, "aclk_vdu", "aclk_vdu_pre", 17, 8), + GATE(0, "hclk_vcodec_noc", "hclk_vcodec_pre", 17, 3), + GATE(HCLK_VCODEC, "hclk_vcodec", "hclk_vcodec_pre", 17, 2), + GATE(0, "aclk_vcodec_noc", "aclk_vcodec_pre", 17, 1), + GATE(ACLK_VCODEC, "aclk_vcodec", "aclk_vcodec_pre", 17, 0), -#define PLL_APLLL 1 -#define PLL_APLLB 2 -#define PLL_DPLL 3 -#define PLL_CPLL 4 -#define PLL_GPLL 5 -#define PLL_NPLL 6 -#define PLL_VPLL 7 + /* CRU_CLKGATE_CON18 */ + GATE(PCLK_CIC, "pclk_cic", "pclk_ddr", 18, 15), + GATE(0, "clk_ddr_mon_timer", "xin24m", 18, 14), + GATE(0, "clk_ddr_mon", "clk_ddrc_div2", 18, 13), + GATE(PCLK_DDR_MON, "pclk_ddr_mon", "pclk_ddr", 18, 12), + GATE(0, "clk_ddr_cic", "clk_ddrc_div2", 18, 11), + GATE(PCLK_CENTER_MAIN_NOC, "pclk_center_main_noc", "pclk_ddr", 18, 10), + GATE(0, "clk_ddrcfg_msch1", "clk_ddrc_div2", 18, 9), + GATE(0, "clk_ddrphy1", "clk_ddrc_div2", 18, 8), + GATE(0, "clk_ddrphy_ctrl1", "clk_ddrc_div2", 18, 7), + GATE(0, "clk_ddrc1", "clk_ddrc_div2", 18, 6), + GATE(0, "clk_ddr1_msch", "clk_ddrc_div2", 18, 5), + GATE(0, "clk_ddrcfg_msch0", "clk_ddrc_div2", 18, 4), + GATE(0, "clk_ddrphy0", "clk_ddrc_div2", 18, 3), + GATE(0, "clk_ddrphy_ctrl0", "clk_ddrc_div2", 18, 2), + GATE(0, "clk_ddrc0", "clk_ddrc_div2", 18, 1), -static struct rk_clk_pll_rate rk3399_pll_rates[] = { - { - .freq = 2208000000, - .refdiv = 1, - .fbdiv = 92, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2184000000, - .refdiv = 1, - .fbdiv = 91, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2160000000, - .refdiv = 1, - .fbdiv = 90, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2136000000, - .refdiv = 1, - .fbdiv = 89, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2112000000, - .refdiv = 1, - .fbdiv = 88, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2088000000, - .refdiv = 1, - .fbdiv = 87, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2064000000, - .refdiv = 1, - .fbdiv = 86, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2040000000, - .refdiv = 1, - .fbdiv = 85, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 2016000000, - .refdiv = 1, - .fbdiv = 84, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1992000000, - .refdiv = 1, - .fbdiv = 83, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1968000000, - .refdiv = 1, - .fbdiv = 82, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1944000000, - .refdiv = 1, - .fbdiv = 81, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1920000000, - .refdiv = 1, - .fbdiv = 80, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1896000000, - .refdiv = 1, - .fbdiv = 79, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1872000000, - .refdiv = 1, - .fbdiv = 78, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1848000000, - .refdiv = 1, - .fbdiv = 77, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1824000000, - .refdiv = 1, - .fbdiv = 76, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1800000000, - .refdiv = 1, - .fbdiv = 75, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1776000000, - .refdiv = 1, - .fbdiv = 74, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1752000000, - .refdiv = 1, - .fbdiv = 73, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1728000000, - .refdiv = 1, - .fbdiv = 72, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1704000000, - .refdiv = 1, - .fbdiv = 71, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1680000000, - .refdiv = 1, - .fbdiv = 70, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1656000000, - .refdiv = 1, - .fbdiv = 69, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1632000000, - .refdiv = 1, - .fbdiv = 68, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1608000000, - .refdiv = 1, - .fbdiv = 67, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1600000000, - .refdiv = 3, - .fbdiv = 200, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1584000000, - .refdiv = 1, - .fbdiv = 66, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1560000000, - .refdiv = 1, - .fbdiv = 65, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1536000000, - .refdiv = 1, - .fbdiv = 64, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1512000000, - .refdiv = 1, - .fbdiv = 63, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1488000000, - .refdiv = 1, - .fbdiv = 62, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1464000000, - .refdiv = 1, - .fbdiv = 61, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1440000000, - .refdiv = 1, - .fbdiv = 60, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1416000000, - .refdiv = 1, - .fbdiv = 59, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1392000000, - .refdiv = 1, - .fbdiv = 58, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1368000000, - .refdiv = 1, - .fbdiv = 57, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1344000000, - .refdiv = 1, - .fbdiv = 56, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1320000000, - .refdiv = 1, - .fbdiv = 55, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1296000000, - .refdiv = 1, - .fbdiv = 54, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1272000000, - .refdiv = 1, - .fbdiv = 53, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1248000000, - .refdiv = 1, - .fbdiv = 52, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1200000000, - .refdiv = 1, - .fbdiv = 50, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1188000000, - .refdiv = 2, - .fbdiv = 99, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1104000000, - .refdiv = 1, - .fbdiv = 46, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1100000000, - .refdiv = 12, - .fbdiv = 550, - .postdiv1 = 1, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1008000000, - .refdiv = 1, - .fbdiv = 84, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 1000000000, - .refdiv = 1, - .fbdiv = 125, - .postdiv1 = 3, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 984000000, - .refdiv = 1, - .fbdiv = 82, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 960000000, - .refdiv = 1, - .fbdiv = 80, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 936000000, - .refdiv = 1, - .fbdiv = 78, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 912000000, - .refdiv = 1, - .fbdiv = 76, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 900000000, - .refdiv = 4, - .fbdiv = 300, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 888000000, - .refdiv = 1, - .fbdiv = 74, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 864000000, - .refdiv = 1, - .fbdiv = 72, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 840000000, - .refdiv = 1, - .fbdiv = 70, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 816000000, - .refdiv = 1, - .fbdiv = 68, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 800000000, - .refdiv = 1, - .fbdiv = 100, - .postdiv1 = 3, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 700000000, - .refdiv = 6, - .fbdiv = 350, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 696000000, - .refdiv = 1, - .fbdiv = 58, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 676000000, - .refdiv = 3, - .fbdiv = 169, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 600000000, - .refdiv = 1, - .fbdiv = 75, - .postdiv1 = 3, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 594000000, - .refdiv = 1, - .fbdiv = 99, - .postdiv1 = 4, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 533250000, - .refdiv = 8, - .fbdiv = 711, - .postdiv1 = 4, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 504000000, - .refdiv = 1, - .fbdiv = 63, - .postdiv1 = 3, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 500000000, - .refdiv = 6, - .fbdiv = 250, - .postdiv1 = 2, - .postdiv2 = 1, - .dsmpd = 1, - }, - { - .freq = 408000000, - .refdiv = 1, - .fbdiv = 68, - .postdiv1 = 2, - .postdiv2 = 2, - .dsmpd = 1, - }, - { - .freq = 312000000, - .refdiv = 1, - .fbdiv = 52, - .postdiv1 = 2, - .postdiv2 = 2, - .dsmpd = 1, - }, - { - .freq = 297000000, - .refdiv = 1, - .fbdiv = 99, - .postdiv1 = 4, - .postdiv2 = 2, - .dsmpd = 1, - }, - { - .freq = 216000000, - .refdiv = 1, - .fbdiv = 72, - .postdiv1 = 4, - .postdiv2 = 2, - .dsmpd = 1, - }, - { - .freq = 148500000, - .refdiv = 1, - .fbdiv = 99, - .postdiv1 = 4, - .postdiv2 = 4, - .dsmpd = 1, - }, - { - .freq = 106500000, - .refdiv = 1, - .fbdiv = 71, - .postdiv1 = 4, - .postdiv2 = 4, - .dsmpd = 1, - }, - { - .freq = 96000000, - .refdiv = 1, - .fbdiv = 64, - .postdiv1 = 4, - .postdiv2 = 4, - .dsmpd = 1, - }, - { - .freq = 74250000, - .refdiv = 2, - .fbdiv = 99, - .postdiv1 = 4, - .postdiv2 = 4, - .dsmpd = 1, - }, - { - .freq = 65000000, - .refdiv = 1, - .fbdiv = 65, - .postdiv1 = 6, - .postdiv2 = 4, - .dsmpd = 1, - }, *** DIFF OUTPUT TRUNCATED AT 1000 LINES ***