From nobody Mon Feb 17 16:36:56 2025 X-Original-To: dev-commits-src-all@mlmmj.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mlmmj.nyi.freebsd.org (Postfix) with ESMTP id 4YxSwm3MMHz5ns11; Mon, 17 Feb 2025 16:36:56 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256 client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "R11" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 4YxSwm2fS3z42Xq; Mon, 17 Feb 2025 16:36:56 +0000 (UTC) (envelope-from git@FreeBSD.org) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1739810216; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=M7sRBQ8BD9JSPj/MoihQr4F8JSr6tH8RYlNQ8IlR1L4=; b=a2sWoZMkOLtuldo3TzcAG+sGIlI1lEzepu6tm4bE64cCozEWTLKiUVEgEFxamw4686o1gK jk3e0UHHwnnbtLYC80NwsrQsDRLbRLq0XMglwxof6pvyiaLMQmhEm9sJoHo0+vyq3whVxl BY5VOrc+Sh5jiCk7wEKcnY9EqUHCjkN+u0yDWABvpIhQWp3MfueA9iH1hwUs7c8AAtsj1h l8DVOAuplrNMDntlwGQg0Me5WWitYzB70l8yt7SVMpknKPn8r73YsMnOCAuOY5pASv2Rnw H7dfeVEw1GjNFgR7dh4BwkDUocRQ9Qt87cwrXDmh+1awqBhGUV8Jxyip5I7zJg== ARC-Seal: i=1; s=dkim; d=freebsd.org; t=1739810216; a=rsa-sha256; cv=none; b=WUKmyoL0dukzUII6L7hAvjlDzGeRZQVhRtARxaK1n7R+9+35aG/K/5EWs5znuayk4B3es2 ba7KoBe0x2F/ijpGSedOB+ZJGcc4usexc46Vn+CNImxjaSYNfviGocx+kKULatSaR3bMnc xx6j0Eq62CRi5OUZATXQsM9JzPVkHVjD46f9HnPaGuQinCW2QgjXIQJg/bDjylk7YtXTWM 43/A5AkVhgOgGjbNh6GXdtJPO4J1s30H5oTkDSHkLuyF7FKZ4L4Tt7dWXAzZErAl7gENyz h0nDzUBdq14u8zzzgffKPieE+cZqt5Qwqom0Jtrr7XjTSLElc1hO5UeNCLEX4g== ARC-Authentication-Results: i=1; mx1.freebsd.org; none ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=freebsd.org; s=dkim; t=1739810216; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding; bh=M7sRBQ8BD9JSPj/MoihQr4F8JSr6tH8RYlNQ8IlR1L4=; b=WMW9C/4o4IO5rzBH+pWLH5G6QH0qHCYglEefIhTiqXCoMMTh70UlPBOv3VgtqfDAqJJ8ml Zza597+O8h8fRPVAkO4Wb8MUg72ZgQqJcs8MfCSawETNLluO3Fig/EY8s0wyo+riEvmOFx TM/c+cJY1HYovEaUjQfHMQK+fKvcQnBPmbjbxAFHJqfXwQZ+65E9/mqu7M69VaYgeQ57CU 2ufGj3pA3eCB746YYnLEovFZ0x+nMHEe5a+EdbGIIsCln8djbKnElyibcheQTMDrahzBWu ZgzJR/fpMVKGEde1EiPw8rzrQg4Ppp8+U3biP6gTX9Ex3ZYxc2hv87VDdegULQ== Received: from gitrepo.freebsd.org (gitrepo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:5]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 4YxSwm1xFJzghw; Mon, 17 Feb 2025 16:36:56 +0000 (UTC) (envelope-from git@FreeBSD.org) Received: from gitrepo.freebsd.org ([127.0.1.44]) by gitrepo.freebsd.org (8.18.1/8.18.1) with ESMTP id 51HGauuM082750; Mon, 17 Feb 2025 16:36:56 GMT (envelope-from git@gitrepo.freebsd.org) Received: (from git@localhost) by gitrepo.freebsd.org (8.18.1/8.18.1/Submit) id 51HGauOM082747; Mon, 17 Feb 2025 16:36:56 GMT (envelope-from git) Date: Mon, 17 Feb 2025 16:36:56 GMT Message-Id: <202502171636.51HGauOM082747@gitrepo.freebsd.org> To: src-committers@FreeBSD.org, dev-commits-src-all@FreeBSD.org, dev-commits-src-main@FreeBSD.org From: Andrew Turner Subject: git: 05f6f65c3bda - main - arm64: add CHECK_CPU_FEAT() for checking feature support in assembly List-Id: Commit messages for all branches of the src repository List-Archive: https://lists.freebsd.org/archives/dev-commits-src-all List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: dev-commits-src-all@freebsd.org Sender: owner-dev-commits-src-all@FreeBSD.org MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit X-Git-Committer: andrew X-Git-Repository: src X-Git-Refname: refs/heads/main X-Git-Reftype: branch X-Git-Commit: 05f6f65c3bdaf241ec819babda666445bf8e9909 Auto-Submitted: auto-generated The branch main has been updated by andrew: URL: https://cgit.FreeBSD.org/src/commit/?id=05f6f65c3bdaf241ec819babda666445bf8e9909 commit 05f6f65c3bdaf241ec819babda666445bf8e9909 Author: Harry Moulton AuthorDate: 2025-02-17 15:58:39 +0000 Commit: Andrew Turner CommitDate: 2025-02-17 16:07:35 +0000 arm64: add CHECK_CPU_FEAT() for checking feature support in assembly Add a new macro under asm.h to check whether a given CPU feature is supported. There are a number of existing places where an ID register is checked, and these have been updated in this change. These are for GIC special registers, HAFDBS and HCX. When calling, pass a temporary registers who's value is not important, the name of the ID register (minus the exception level), the name of the feature, and a label to jump to should the feature not be present. The feature name should match with the macros defined in armreg.h or hypervisor.h. Any feature-specific instructions can then be placed between the macro and the label. Reviewed by: andrew Sponsored by: Arm Ltd Differential Revision: https://reviews.freebsd.org/D48813 Signed-off-by: Harry Moulton --- sys/arm64/arm64/locore.S | 17 ++++------------- sys/arm64/include/asm.h | 10 ++++++++++ 2 files changed, 14 insertions(+), 13 deletions(-) diff --git a/sys/arm64/arm64/locore.S b/sys/arm64/arm64/locore.S index f3b846eee412..88193b6c93f7 100644 --- a/sys/arm64/arm64/locore.S +++ b/sys/arm64/arm64/locore.S @@ -403,10 +403,7 @@ LENTRY(enter_kernel_el) * Configure the Extended Hypervisor register. This is only valid if * FEAT_HCX is enabled. */ - mrs x2, id_aa64mmfr1_el1 - ubfx x2, x2, #ID_AA64MMFR1_HCX_SHIFT, #ID_AA64MMFR1_HCX_WIDTH - cbz x2, 2f - + CHECK_CPU_FEAT(x2, ID_AA64MMFR1, HCX, 2f) /* Extended Hypervisor Configuration */ mov x2, xzr msr HCRX_EL2_REG, x2 @@ -422,12 +419,8 @@ LENTRY(enter_kernel_el) /* Zero vttbr_el2 so a hypervisor can tell the host and guest apart */ msr vttbr_el2, xzr - /* Configure GICv3 CPU interface */ - mrs x2, id_aa64pfr0_el1 - /* Extract GIC bits from the register */ - ubfx x2, x2, #ID_AA64PFR0_GIC_SHIFT, #ID_AA64PFR0_GIC_BITS - /* GIC[3:0] != 0000 - GIC CPU interface via special regs. supported */ - cbz x2, 3f + /* Check the CPU supports GIC, and configure the CPU interface */ + CHECK_CPU_FEAT(x2, ID_AA64PFR0, GIC, 3f) mrs x2, icc_sre_el2 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */ @@ -958,9 +951,7 @@ LENTRY(start_mmu) * HW management of dirty state is set in C code as it may * need to be disabled because of CPU errata. */ - mrs x3, id_aa64mmfr1_el1 - and x3, x3, #(ID_AA64MMFR1_HAFDBS_MASK) - cbz x3, 1f + CHECK_CPU_FEAT(x3, ID_AA64MMFR1, HAFDBS, 1f) orr x2, x2, #(TCR_HA) 1: diff --git a/sys/arm64/include/asm.h b/sys/arm64/include/asm.h index cc0a7d8293c9..4f373dc4b7e1 100644 --- a/sys/arm64/include/asm.h +++ b/sys/arm64/include/asm.h @@ -72,6 +72,16 @@ /* Alias for link register x30 */ #define lr x30 +/* + * Check whether a given cpu feature is present, in the case it is not we jump + * to the given label. The tmp register should be a register able to hold the + * temporary data. + */ +#define CHECK_CPU_FEAT(tmp, feat_reg, feat, label) \ + mrs tmp, ##feat_reg##_el1; \ + ubfx tmp, tmp, ##feat_reg##_##feat##_SHIFT, ##feat_reg##_##feat##_WIDTH; \ + cbz tmp, label + /* * Sets the trap fault handler. The exception handler will return to the * address in the handler register on a data abort or the xzr register to