From owner-svn-src-all@FreeBSD.ORG Mon Jul 7 05:17:17 2014 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id 9497C73A; Mon, 7 Jul 2014 05:17:17 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8219429BB; Mon, 7 Jul 2014 05:17:17 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.8/8.14.8) with ESMTP id s675HHbP048972; Mon, 7 Jul 2014 05:17:17 GMT (envelope-from hselasky@svn.freebsd.org) Received: (from hselasky@localhost) by svn.freebsd.org (8.14.8/8.14.8/Submit) id s675HHr9048970; Mon, 7 Jul 2014 05:17:17 GMT (envelope-from hselasky@svn.freebsd.org) Message-Id: <201407070517.s675HHr9048970@svn.freebsd.org> From: Hans Petter Selasky Date: Mon, 7 Jul 2014 05:17:17 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r268354 - head/sys/dev/usb/controller X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 07 Jul 2014 05:17:17 -0000 Author: hselasky Date: Mon Jul 7 05:17:16 2014 New Revision: 268354 URL: http://svnweb.freebsd.org/changeset/base/268354 Log: Improve support for Intel Lynx Point USB 3.0 controllers by masking the port routing bits like done in Linux. MFC after: 1 week Tested by: Tur-Wei Chan Modified: head/sys/dev/usb/controller/xhci_pci.c head/sys/dev/usb/controller/xhcireg.h Modified: head/sys/dev/usb/controller/xhci_pci.c ============================================================================== --- head/sys/dev/usb/controller/xhci_pci.c Mon Jul 7 03:10:56 2014 (r268353) +++ head/sys/dev/usb/controller/xhci_pci.c Mon Jul 7 05:17:16 2014 (r268354) @@ -157,6 +157,9 @@ xhci_pci_port_route(device_t self, uint3 temp |= set; temp &= ~clear; + /* Don't set bits which the hardware doesn't support */ + temp &= pci_read_config(self, PCI_XHCI_INTEL_USB3PRM, 4); + pci_write_config(self, PCI_XHCI_INTEL_USB3_PSSEN, temp, 4); pci_write_config(self, PCI_XHCI_INTEL_XUSB2PR, temp, 4); Modified: head/sys/dev/usb/controller/xhcireg.h ============================================================================== --- head/sys/dev/usb/controller/xhcireg.h Mon Jul 7 03:10:56 2014 (r268353) +++ head/sys/dev/usb/controller/xhcireg.h Mon Jul 7 05:17:16 2014 (r268354) @@ -35,7 +35,9 @@ #define PCI_XHCI_FLADJ 0x61 /* RW frame length adjust */ #define PCI_XHCI_INTEL_XUSB2PR 0xD0 /* Intel USB2 Port Routing */ +#define PCI_XHCI_INTEL_USB2PRM 0xD4 /* Intel USB2 Port Routing Mask */ #define PCI_XHCI_INTEL_USB3_PSSEN 0xD8 /* Intel USB3 Port SuperSpeed Enable */ +#define PCI_XHCI_INTEL_USB3PRM 0xDC /* Intel USB3 Port Routing Mask */ /* XHCI capability registers */ #define XHCI_CAPLENGTH 0x00 /* RO capability */