From owner-svn-ports-all@FreeBSD.ORG Sun Aug 5 04:57:55 2012 Return-Path: Delivered-To: svn-ports-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id A6B4C1065672; Sun, 5 Aug 2012 04:57:55 +0000 (UTC) (envelope-from miwi@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 90E1D8FC08; Sun, 5 Aug 2012 04:57:55 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q754vtrA037553; Sun, 5 Aug 2012 04:57:55 GMT (envelope-from miwi@svn.freebsd.org) Received: (from miwi@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q754vtUM037548; Sun, 5 Aug 2012 04:57:55 GMT (envelope-from miwi@svn.freebsd.org) Message-Id: <201208050457.q754vtUM037548@svn.freebsd.org> From: Martin Wilke Date: Sun, 5 Aug 2012 04:57:55 +0000 (UTC) To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org X-SVN-Group: ports-head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r302051 - head/cad/verilog-mode.el X-BeenThere: svn-ports-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the ports tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 05 Aug 2012 04:57:55 -0000 Author: miwi Date: Sun Aug 5 04:57:54 2012 New Revision: 302051 URL: http://svn.freebsd.org/changeset/ports/302051 Log: - Update to 801 PR: 170139 Submitted by: Ports Fury Modified: head/cad/verilog-mode.el/Makefile head/cad/verilog-mode.el/distinfo head/cad/verilog-mode.el/pkg-descr head/cad/verilog-mode.el/pkg-plist Modified: head/cad/verilog-mode.el/Makefile ============================================================================== --- head/cad/verilog-mode.el/Makefile Sun Aug 5 04:53:22 2012 (r302050) +++ head/cad/verilog-mode.el/Makefile Sun Aug 5 04:57:54 2012 (r302051) @@ -6,28 +6,30 @@ # PORTNAME= verilog-mode.el -PORTVERSION= 790 +PORTVERSION= 801 CATEGORIES= cad elisp MASTER_SITES= http://www.veripool.org/ftp/ -DISTNAME= verilog-mode-${PORTVERSION}.el +DISTNAME= ${PORTNAME:R}-${PORTVERSION}.${PORTNAME:E} EXTRACT_SUFX= .gz MAINTAINER= ports@FreeBSD.org COMMENT= Emacs lisp modules for the Verilog language +LICENSE= GPLv3 # (or later) + +EXTRACT_AFTER_ARGS= > ${PORTNAME} + +NO_WRKSUBDIR= yes NO_BUILD= yes -EXTRACT_AFTER_ARGS= > ${ELFILE} -ELFILE= verilog-mode.el -EMACSLISPDIR= ${PREFIX}/share/emacs/site-lisp -XEMACSLISPDIR= ${PREFIX}/lib/xemacs/site-lisp +USE_EMACS= yes +EMACS_NO_BUILD_DEPENDS= yes + +PLIST_FILES= ${EMACS_SITE_LISPDIR}/${PORTNAME} do-install: - ${MKDIR} ${DATADIR}/ - ${INSTALL_DATA} ${WRKDIR}/${ELFILE} ${DATADIR}/ - ${MKDIR} ${XEMACSLISPDIR} - ${LN} -sf ${DATADIR}/${ELFILE} ${EMACSLISPDIR}/ - ${LN} -sf ${DATADIR}/${ELFILE} ${XEMACSLISPDIR}/ + @${MKDIR} ${PREFIX}/${EMACS_SITE_LISPDIR} + ${INSTALL_DATA} ${WRKSRC}/${PORTNAME} ${PREFIX}/${EMACS_SITE_LISPDIR} @${CAT} ${PKGMESSAGE} .include Modified: head/cad/verilog-mode.el/distinfo ============================================================================== --- head/cad/verilog-mode.el/distinfo Sun Aug 5 04:53:22 2012 (r302050) +++ head/cad/verilog-mode.el/distinfo Sun Aug 5 04:57:54 2012 (r302051) @@ -1,2 +1,2 @@ -SHA256 (verilog-mode-790.el.gz) = eca9dd11500dce962b51a42e7c89a0dc414bea3a3dd79a2daf94286c8ad3d729 -SIZE (verilog-mode-790.el.gz) = 114783 +SHA256 (verilog-mode-801.el.gz) = 38004b5b222c6bbbe743af629cbbfc2a8fbc5706567996f813d73f708fe61e16 +SIZE (verilog-mode-801.el.gz) = 115719 Modified: head/cad/verilog-mode.el/pkg-descr ============================================================================== --- head/cad/verilog-mode.el/pkg-descr Sun Aug 5 04:53:22 2012 (r302050) +++ head/cad/verilog-mode.el/pkg-descr Sun Aug 5 04:57:54 2012 (r302051) @@ -2,9 +2,9 @@ Verilog-mode.el is a Verilog mode for Em highlighting, auto indenting, and provides macro expansion capabilities to greatly reduce Verilog coding time. -Recent versions allow you to insert AUTOS in non-AUTO designs, so IP interconnect -can be easily modified. You can also expand Verilog-2001 ".*" instantiations, to -see what ports will be connected by simulators. +Recent versions allow you to insert AUTOS in non-AUTO designs, so IP +interconnect can be easily modified. You can also expand Verilog-2001 ".*" +instantiations, to see what ports will be connected by simulators. Author: Michael McNamara , Wilson Snyder WWW: http://www.veripool.org/wiki/verilog-mode Modified: head/cad/verilog-mode.el/pkg-plist ============================================================================== --- head/cad/verilog-mode.el/pkg-plist Sun Aug 5 04:53:22 2012 (r302050) +++ head/cad/verilog-mode.el/pkg-plist Sun Aug 5 04:57:54 2012 (r302051) @@ -1,6 +0,0 @@ -share/emacs/site-lisp/verilog-mode.el -lib/xemacs/site-lisp/verilog-mode.el -%%DATADIR%%/verilog-mode.el -@dirrmtry lib/xemacs/site-lisp -@dirrmtry lib/xemacs -@dirrm %%DATADIR%%