From owner-freebsd-sparc64@FreeBSD.ORG Wed Jul 2 08:40:24 2003 Return-Path: Delivered-To: freebsd-sparc64@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A1DDC37B401 for ; Wed, 2 Jul 2003 08:40:24 -0700 (PDT) Received: from k6.locore.ca (k6.locore.ca [198.96.117.170]) by mx1.FreeBSD.org (Postfix) with ESMTP id EDC2A43F85 for ; Wed, 2 Jul 2003 08:40:23 -0700 (PDT) (envelope-from jake@locore.ca) Received: by k6.locore.ca (Postfix, from userid 1000) id 2B04414F86; Wed, 2 Jul 2003 11:40:02 -0400 (EDT) Date: Wed, 2 Jul 2003 11:40:02 -0400 From: Jake Burkholder To: Marcel Moolenaar , sparc64@freebsd.org Message-ID: <20030702154002.GA40152@k6.locore.ca> References: <20030702040139.GA11199@dhcp01.pn.xcllnt.net> <20030702040928.GC58048@funkthat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20030702040928.GC58048@funkthat.com> User-Agent: Mutt/1.4.1i Subject: Re: OFW_NEWPCI dmesg diffs X-BeenThere: freebsd-sparc64@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Porting FreeBSD to the Sparc List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 02 Jul 2003 15:40:25 -0000 Apparently, On Tue, Jul 01, 2003 at 09:09:28PM -0700, John-Mark Gurney said words to the effect of; > Marcel Moolenaar wrote this message on Tue, Jul 01, 2003 at 21:01 -0700: > > BTW: vmstat -i doesn't work: > > > > sparc% vmstat -i > > interrupt total rate > > Total 0 0 > > sparc% > > I have patches to fix this. > > But, I the problem is that both soft interrupts and vector interrupts > are useful to know. All vector interrupts are dispatched via soft > interrupts, so if we count both, the interrupt count is double. We > need soft interrupts if we want to see the clock ticking. > > bash-2.05b$ vmstat -i > interrupt total rate > stray 1 0 > pil 1 0 > ithrd pil2 69163 16 > gem0 vec2012 27748 6 > gem1 vec1990 70 0 > atapci0 vec1996 41345 9 > tick pil14 421278 99 > Total 559606 132 > > notice that ithrd is equal to gem0 + gem1 + atapci0. pil is the > priority interrupt level (aka soft interrupts). > > Comments? Do we count both? or not include soft interrupts? or not > include the ithrd pil? I think counting both is fine for now. Eventually what I intend to do is change tick handling so that it looks more like a vectored interrupt. The pil14 handler would queue and reprioritize the tick interrupts so that tick can be re-armed independent of the handler actually running. The soft interrupt that drives hardclock would have a vector number (outside of the normal 11 bits for hardware interrupts), and be counted uniformly. Jake