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Date: Wed, 1 Mar 2006 11:38:03 -0500
From: Andrew Gallatin <gallatin@cs.duke.edu>
To: Scott Long <scottl@samsco.org>
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	from scottl@samsco.org on Tue, Feb 28, 2006 at 03:49:34PM -0700
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Cc: cvs-src@FreeBSD.org, src-committers@FreeBSD.org, cvs-all@FreeBSD.org,
	John Baldwin <jhb@FreeBSD.org>
Subject: Re: cvs commit: src/sys/amd64/amd64 intr_machdep.c io_apic.c
	local_apic.c mp_machdep.c src/sys/amd64/include apicvar.h
	intr_machdep.h src/sys/amd64/isa atpic.c src/sys/i386/i386
	intr_machdep.c io_apic.c local_apic.c mp_machdep.c ...
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Scott Long [scottl@samsco.org] wrote:
<...>
>   Also, it's not so
> much important which CPU gets the interrupt as it is which CPU runs the
> ithread for that interrupt.  I guess that you can get a little better
> latency by preempting directly from the low-level interrupt handler into
> the ithread, but I don't know if that is noticable noise above the cost
> of the context switch and inevitable lock operations and contention
> involved.

What do you mean by "preempting directly from the low-level interrupt
handler into the ithread" ?  Do you mean running the ithread directly
in the context of the hardware interrupt until it does something where
it needed to block?  Do we do this now?

Thanks,

Drew