Date: Thu, 16 Mar 2006 08:59:10 GMT From: Kip Macy <kmacy@FreeBSD.org> To: Perforce Change Reviews <perforce@freebsd.org> Subject: PERFORCE change 93390 for review Message-ID: <200603160859.k2G8xAvU050511@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=93390 Change 93390 by kmacy@kmacy_storage:sun4v_work on 2006/03/16 08:58:10 add support for vm faults during register spill / fill handling Affected files ... .. //depot/projects/kmacy_sun4v/src/sys/sparc64/sparc64/genassym.c#10 edit .. //depot/projects/kmacy_sun4v/src/sys/sun4v/include/trap.h#4 edit .. //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#31 edit Differences ... ==== //depot/projects/kmacy_sun4v/src/sys/sparc64/sparc64/genassym.c#10 (text+ko) ==== @@ -335,3 +335,4 @@ ASSYM(TF_SIZEOF, sizeof(struct trapframe)); ASSYM(UT_MAX, UT_MAX); +ASSYM(VM_MIN_DIRECT_ADDRESS, VM_MIN_DIRECT_ADDRESS); ==== //depot/projects/kmacy_sun4v/src/sys/sun4v/include/trap.h#4 (text+ko) ==== @@ -31,6 +31,8 @@ #ifdef _KERNEL +#define T_ALIGNMENT 0x34 + #define T_RESERVED 0 #define T_INSTRUCTION_EXCEPTION 1 #define T_INSTRUCTION_ERROR 2 @@ -106,6 +108,18 @@ #define PTL1_BAD_HCALL 14 #define PTL1_BAD_GL 15 + +/* + * These defines are used by the TL1 tlb miss handlers to calculate + * the pc to jump to in the case the entry was not found in the TSB. + */ +#define WTRAP_ALIGN 0x7f /* window handlers are 128 byte align */ +#define WTRAP_FAULTOFF 124 /* last instruction in handler */ + +/* use the following defines to determine if trap was a fill or a spill */ +#define WTRAP_TTMASK 0x180 +#define WTRAP_TYPE 0x080 + #ifndef LOCORE extern const char *trap_msg[]; void trap_init(void); ==== //depot/projects/kmacy_sun4v/src/sys/sun4v/sun4v/exception.S#31 (text+ko) ==== @@ -74,7 +74,7 @@ #define PCB_REG %g6 -#include <sun4v/sun4v/wbuf.S> + /* @@ -104,7 +104,26 @@ * */ -#define SPILL(storer, bias, size, asi) \ + +#define SPILL(storer, base, size) \ + storer %l0, [base + (0 * size)] ; \ + storer %l1, [base + (1 * size)] ; \ + storer %l2, [base + (2 * size)] ; \ + storer %l3, [base + (3 * size)] ; \ + storer %l4, [base + (4 * size)] ; \ + storer %l5, [base + (5 * size)] ; \ + storer %l6, [base + (6 * size)] ; \ + storer %l7, [base + (7 * size)] ; \ + storer %i0, [base + (8 * size)] ; \ + storer %i1, [base + (9 * size)] ; \ + storer %i2, [base + (10 * size)] ; \ + storer %i3, [base + (11 * size)] ; \ + storer %i4, [base + (12 * size)] ; \ + storer %i5, [base + (13 * size)] ; \ + storer %i6, [base + (14 * size)] ; \ + storer %i7, [base + (15 * size)] + +#define SPILL_ASI(storer, bias, size, asi) \ mov 0 + bias, %g1 ;\ storer %l0, [%sp + %g1]asi ;\ mov size + bias, %g2 ;\ @@ -169,6 +188,7 @@ ldda [%g3 + %g1]asi, %i4 ;\ ldda [%g3 + %g2]asi, %i6 +#include <sun4v/sun4v/wbuf.S> /* * Clean window traps occur when %cleanwin is zero to ensure that data * is not leaked between address spaces in registers. @@ -344,7 +364,7 @@ #define spill_32bit_asi(asi, target) \ srl %sp, 0, %sp ; \ SPILL_FILL_MAGIC_TRAP_ON; \ - SPILL(sta, 0, 4, asi) ; \ + SPILL_ASI(sta, 0, 4, asi) ; \ saved ; \ SPILL_FILL_MAGIC_TRAP_OFF; \ retry ; \ @@ -354,7 +374,7 @@ #define spill_64bit_asi(asi, target) \ SPILL_FILL_MAGIC_TRAP_ON ; \ - SPILL(stxa, SPOFF, 8, asi) ; \ + SPILL_ASI(stxa, SPOFF, 8, asi) ; \ saved ; \ SPILL_FILL_MAGIC_TRAP_OFF ; \ retry ; \ @@ -365,7 +385,7 @@ #define spill_32clean(asi, target) \ srl %sp, 0, %sp ; \ SPILL_FILL_MAGIC_TRAP_ON; \ - SPILL(sta, 0, 4, asi) ; \ + SPILL_ASI(sta, 0, 4, asi) ; \ b spill_clean ; \ mov WSTATE_USER32, %g7 ; \ .skip (31-27)*4 ; \ @@ -374,7 +394,7 @@ #define spill_64clean(asi, target) \ SPILL_FILL_MAGIC_TRAP_ON; \ - SPILL(stxa, SPOFF, 8, asi) ; \ + SPILL_ASI(stxa, SPOFF, 8, asi) ; \ b spill_clean ; \ mov WSTATE_USER64, %g7 ; \ .skip (31-26)*4 ; \ @@ -706,19 +726,23 @@ spill_64bit_nucleus_not ! 0x98 tl0_spill_7_normal: spill_mixed ! 0x9c -tl0_spill_n_other_a0: +tl0_spill_0_other: tl0_reserved 4 ! 0xa0 -tl0_spill_n_other_a4: +tl0_spill_1_other: spill_32bit_secondary_so0 ! 0xa4 -tl0_spill_n_other_a8: +tl0_spill_2_other: spill_64bit_secondary_so0 ! 0xa8 -tl0_spill_n_other_ac: +tl0_spill_3_other: spill_32bit_secondary_so0 ! 0xac -tl0_spill_n_other_b0: +tl0_spill_4_other: spill_64bit_secondary_so0 ! 0xb0 -tl0_spill_n_other_b4: - tl0_reserved 12 ! 0xb4-0xbf -tl0_fill_n_normal_c0: +tl0_spill_5_other: + tl0_reserved 4 ! 0xb4 +tl0_spill_6_other: + tl0_reserved 4 ! 0xb8 +tl0_spill_7_other: + tl0_reserved 4 ! 0xbc +tl0_fill_n_normal: tl0_reserved 4 ! 0xc0 fill_32bit_primary_fn0 ! 0xc4 fill_64bit_primary_fn0 ! 0xc8 @@ -953,7 +977,8 @@ ba,a,pt %xcc, user_rtt nop -1: ldx [PCB_REG + PCB_NSAVED], %l1 +1: GET_PCB(PCB_REG) + ldx [PCB_REG + PCB_NSAVED], %l1 brz,a,pt %l1, 2f nop wrpr %g0, 0, %pil @@ -1074,7 +1099,7 @@ wrpr %g0, %g1, %cleanwin rdpr %cwp, %g1 wrpr %g1, %g7, %tstate -! MAGIC_TRAP_ON + MAGIC_TRAP_ON retry END(user_rtt) END(utl0) @@ -1200,6 +1225,13 @@ ! %l7 trapframe ENTRY(tl0_trap) + MAGIC_TRAP_OFF + /* if we're at tl2 we have some extra work to do */ + rdpr %tl, %g5 + cmp %g5, 2 + be,pn %xcc, tl1_trap + nop + rdpr %tstate, %g5 btst TSTATE_PRIV, %g5 and %g5, TSTATE_CWP_MASK, %g6 @@ -1322,7 +1354,16 @@ bne,pn %xcc, 17f nop ! MAGIC_TRAP_ON ! enable debugging for instruction misses -17: +17: + sethi %uhi(VM_MIN_DIRECT_ADDRESS), %g7 + sllx %g7, 32, %g7 + cmp %g5, %g7 + blu %xcc, 7f + nop + MAGIC_TRAP_ON + MAGIC_EXIT +7: + #endif tsb_miss_compute_hash_addr: @@ -1392,12 +1433,6 @@ ! we need to jump to tl0_trap to drop us back down to tl0 ! and take us to trap(...) to service the fault #ifdef PMAP_DEBUG - rdpr %tl, %g4 - cmp %g4, 1 - be,pt %xcc, 15f - nop - MAGIC_TRAP_ON;MAGIC_TRAP_ON;MAGIC_EXIT -15: #if 0 srlx %g6, TTARGET_CTX_SHIFT, %g4 ! recover context brnz %g4, 16f @@ -1558,8 +1593,54 @@ .comm intrcnt, IV_MAX * 8 .comm eintrcnt, 0 - +#define TRAP_ENTRY_SHIFT 5 +#define TRAP_ENTRY_MASK 0x1ff ENTRY(tl1_trap) - MAGIC_TRAP_ON;MAGIC_TRAP_ON;MAGIC_EXIT + ! MAGIC_TRAP_ON + ! assume no tl1 handler + rdpr %tpc, %g7 + + set rtt_fill_start, %g6 + cmp %g7, %g6 + blu,pn %xcc, 1f + .empty + set rtt_fill_end, %g6 + cmp %g7, %g6 + bgeu,pn %xcc, 1f + nop + set fault_rtt_fn1, %g7 + ba,a 2f +1: + set tl1_end, %g6 + cmp %g7, %g6 + bgeu,a,pn %xcc, ptl1_panic + mov PTL1_BAD_TRAP, %g1 + ! tpc is in the trap table + ! convert to trap index + srl %g7, TRAP_ENTRY_SHIFT, %g6 + and %g6, TRAP_ENTRY_MASK, %g6 + ! check for window trap type + and %g6, WTRAP_TTMASK, %g6 + cmp %g6, WTRAP_TYPE + bne,a,pn %xcc, ptl1_panic + mov PTL1_BAD_TRAP, %g1 + andn %g7, WTRAP_ALIGN, %g7 + add %g7, WTRAP_FAULTOFF, %g7 +2: + wrpr %g0, %g7, %tnpc + wrpr %g0, 1, %gl + rdpr %tt, %g5 + GET_MMFSA_SCRATCH(%g7) + cmp %g5, T_ALIGNMENT + be,pn %xcc, 3f + wr %g0, ASI_REAL, %asi + ldxa [%g7 + MMFSA_D_ADDR]%asi, %g6 + ldxa [%g7 + MMFSA_D_CTX]%asi, %g7 + srlx %g6, PAGE_SHIFT, %g6 + sllx %g6, PAGE_SHIFT, %g6 ! mask off bottom + or %g6, %g7, %g6 + +3: + done END(tl1_trap)
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