Date: Thu, 18 Oct 2018 16:27:37 +0100 From: Ruslan Bukin <ruslan.bukin@cl.cam.ac.uk> To: Ian Lepore <ian@freebsd.org> Cc: Ruslan Bukin <br@FreeBSD.org>, src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: Re: svn commit: r339421 - in head/sys: arm/arm arm/conf dts/arm riscv/include riscv/riscv Message-ID: <20181018152737.GA53601@bsdpad.com> In-Reply-To: <1539875600.86290.14.camel@freebsd.org> References: <201810181508.w9IF8FfX034673@repo.freebsd.org> <1539875600.86290.14.camel@freebsd.org>
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On Thu, Oct 18, 2018 at 09:13:20AM -0600, Ian Lepore wrote: > On Thu, 2018-10-18 at 15:08 +0000, Ruslan Bukin wrote: > > Author: br > > Date: Thu Oct 18 15:08:14 2018 > > New Revision: 339421 > > URL: https://svnweb.freebsd.org/changeset/base/339421 > > > > Log: > > Support RISC-V implementations that do not manage the A and D bits > > (e.g. RocketChip, lowRISC and derivatives). > > > > RISC-V page table entries support A (accessed) and D (dirty) bits. The > > spec makes hardware support for these bits optional. Implementations that > > do not manage these bits in hardware raise page faults for accesses to a > > valid page without A set and writes to a writable page without D set. > > Check for these types of faults when handling a page fault and fixup the > > PTE without calling vm_fault if they occur. > > > > Reviewed by: jhb, markj > > Approved by: re (gjb) > > Sponsored by: DARPA, AFRL > > Differential Revision: https://reviews.freebsd.org/D17424 > > > > Modified: > > head/sys/arm/arm/pl310.c > > head/sys/arm/conf/GENERIC > > head/sys/arm/conf/GENERIC-MMCCAM > > head/sys/arm/conf/SOCDK > > head/sys/dts/arm/socfpga_arria10_socdk_sdmmc.dts > > head/sys/riscv/include/pmap.h > > head/sys/riscv/include/pte.h > > head/sys/riscv/riscv/locore.S > > head/sys/riscv/riscv/pmap.c > > head/sys/riscv/riscv/trap.c > > > > It looks like some unintended arm files got included in this commit. > Thanks, fixed! Ruslan
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