From owner-freebsd-hackers Tue Aug 29 19:33:23 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.FreeBSD.org (8.6.11/8.6.6) id TAA04150 for hackers-outgoing; Tue, 29 Aug 1995 19:33:23 -0700 Received: from gndrsh.aac.dev.com (gndrsh.aac.dev.com [198.145.92.241]) by freefall.FreeBSD.org (8.6.11/8.6.6) with ESMTP id TAA04132 for ; Tue, 29 Aug 1995 19:32:55 -0700 Received: (from rgrimes@localhost) by gndrsh.aac.dev.com (8.6.11/8.6.9) id TAA05628; Tue, 29 Aug 1995 19:31:38 -0700 From: "Rodney W. Grimes" Message-Id: <199508300231.TAA05628@gndrsh.aac.dev.com> Subject: Re: S.O.S -2.1Stable and ASUSP54TP4 To: bde@zeta.org.au (Bruce Evans) Date: Tue, 29 Aug 1995 19:31:38 -0700 (PDT) Cc: leo@lisa.rur.com, freebsd-hackers@FreeBSD.ORG, jbryant@argus.iadfw.net, rashid@haven.ios.com In-Reply-To: <199508292149.HAA02386@godzilla.zeta.org.au> from "Bruce Evans" at Aug 30, 95 07:49:56 am X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 1617 Sender: hackers-owner@FreeBSD.ORG Precedence: bulk > > >And to state my reason for agreement that parity is a ``itsy-bitsy comfort'', > >think about the fact that 80% of your memory access are going to a L2 > >cache that has never had parity on it, yet has a same FIT rate as the > >main memory system. Basically your more likely today to take a single > >bit error in your cache as you are in main memory :-(. > > Is there anything to detect or correct errors in the registers or > control logic? The Pentium data books are not specific on this issue. I can not publically disclose that information due to NDA's. I can say that the description of signal IERR# would lead you to reasonable conclusions: IERR#, Type Output: The internal error pin is used to indicate two types of errors, internal parity errors and functional redundancy errors. If a parity error occurs on a read from an internal array, the Pentium processor will assert the IERR# pin for one clock and then shutdown. If the Pentium processor is configured as a checker and a mismatch occurs between the value sampled on the pins and the corresponding value computed internally, the Pentium process will assert IERR# two clocks after the mismatched value is returned. Source: ``Pentium(TM) Processors and Related Products'', Intel Corporation, 1995. Order #241732, ISBN 1-55512-239-6. For full detection of register and control logic errors you run 2 Pentiums in fucntional redudancy mode. I am aware of products that do just that. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD