From owner-freebsd-hackers Wed Dec 12 3: 2:37 2001 Delivered-To: freebsd-hackers@freebsd.org Received: from albatross.prod.itd.earthlink.net (albatross.mail.pas.earthlink.net [207.217.120.120]) by hub.freebsd.org (Postfix) with ESMTP id 980CF37B41B; Wed, 12 Dec 2001 03:02:34 -0800 (PST) Received: from pool0012.cvx22-bradley.dialup.earthlink.net ([209.179.198.12] helo=mindspring.com) by albatross.prod.itd.earthlink.net with esmtp (Exim 3.33 #1) id 16E79R-0001n6-00; Wed, 12 Dec 2001 03:02:13 -0800 Message-ID: <3C17393B.8297E824@mindspring.com> Date: Wed, 12 Dec 2001 03:02:19 -0800 From: Terry Lambert X-Mailer: Mozilla 4.7 [en]C-CCK-MCD {Sony} (Win98; U) X-Accept-Language: en MIME-Version: 1.0 To: Warner Losh Cc: Danny Braniss , Bernd Walter , Mike Smith , freebsd-hackers@FreeBSD.ORG Subject: Re: irq References: <3C1614D5.B5C3B4C5@mindspring.com> <200112120516.fBC5GJM33101@harmony.village.org> Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Sender: owner-freebsd-hackers@FreeBSD.ORG Precedence: bulk List-ID: List-Archive: (Web Archive) List-Help: (List Instructions) List-Subscribe: List-Unsubscribe: X-Loop: FreeBSD.ORG Warner Losh wrote: > In message <3C1614D5.B5C3B4C5@mindspring.com> Terry Lambert writes: > : Some cards do not have a hardware "I caused an interrupt" register, > : and use a differential (e.g. ring head vs. tail inequal after > : interrupt) to tell if there is work to do. If these cards were to > : share interrupts, then they most likely do work every interrupt, > : and less work per interrupt, then would otherwise be the case (i.e. > : it would defeat hardware interrupt coelescing thresholds, among > : other things). > > No such PCI cards can exists. The PCI spec requires that interrupt > sharing work. ??? How is setting a local register when an interrupt is triggered antithetical to such cards working? I know of several network cards where I've personally hacked on the driver that have such a register. It's not possbile to take a shared interrupt and not run the ISR, but it's possible for the ISR to check the register and decide on that basis, rather than on data availability, that it will or will not do work. I think that everyone now "gets" that PCI interrupts are like signals, in that they are persistant conditions, so more than one card asserting them doesn't change the fact that "an interrupt" was asserted, and there's no way to tell _from the interrupt_ which cards did or did not assert it in the first place. But we are talking about an extra hardware register on the card that the card sets when it asserts an interrupt, so an ISR can look to ask the card "did you assert an interrupt?" and decide not to process if the answer is "no". The Tigon II interrupt sharing in fact depends on this, or when you had two Tigon II cards, you migh spend the rest of eternity in the ISR. -- Terry To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-hackers" in the body of the message