From owner-freebsd-arm@FreeBSD.ORG Sat Aug 3 22:15:42 2013 Return-Path: Delivered-To: arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 21F699A6 for ; Sat, 3 Aug 2013 22:15:42 +0000 (UTC) (envelope-from ray@freebsd.org) Received: from smtp.dlink.ua (smtp.dlink.ua [193.138.187.146]) by mx1.freebsd.org (Postfix) with ESMTP id CFBC92F9A for ; Sat, 3 Aug 2013 22:15:41 +0000 (UTC) Received: from rnote.ddteam.net (33-33-135-95.pool.ukrtel.net [95.135.33.33]) (Authenticated sender: ray) by smtp.dlink.ua (Postfix) with ESMTPSA id D8AA9C4936; Sun, 4 Aug 2013 01:15:39 +0300 (EEST) Date: Sun, 4 Aug 2013 01:15:35 +0300 From: Aleksandr Rybalko To: Warner Losh Subject: Re: PATCH: get_cyclecount() on ARMv6 and better Message-Id: <20130804011535.b87e1f39.ray@freebsd.org> In-Reply-To: <9342F2DA-2A30-4209-B8C6-A43F194852DA@bsdimp.com> References: <78D22A66-86E5-43B1-ABCA-7BF14F8061AB@grondar.org> <20130803145135.38196156.ray@freebsd.org> <9342F2DA-2A30-4209-B8C6-A43F194852DA@bsdimp.com> Organization: FreeBSD.ORG X-Mailer: Sylpheed 3.1.2 (GTK+ 2.24.5; amd64-portbld-freebsd9.0) X-Operating-System: FreeBSD Mime-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Cc: "freebsd-arm@freebsd.org" , Mark R V Murray X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 03 Aug 2013 22:15:42 -0000 On Sat, 3 Aug 2013 12:01:14 -0600 Warner Losh wrote: > > On Aug 3, 2013, at 6:26 AM, Mark R V Murray wrote: > > > > > On 3 Aug 2013, at 12:51, Aleksandr Rybalko wrote: > >> Hi Mark! > >> > >> Do we setup Performance Monitor Control Register before use that > >> counter? > > > > I've read up on PNMC register now, an looked for it in the code, > > and unless it is very well hidden, then NO, we don't set it up. > > > > I've read now what I need to do; where is the best place do do it? > > I suspect it should be in start-up code right when the ARM is > > starting up; is that a good guess? > > I'd make a timecounter for this, and put that in its initialization > code. > > Warner Since it's PMU register, then better to do PMU driver for it, even if it will have only one feature - read counter. Otherwise you can't depend on it, because you can't guarantee that nobody not disable PMU after use. Another potential useful thing, not to close it under #ifdef ARMv6, but check ARM processor Feature registers. MRC p15, 0, , c0, c1, 2; Read Debug Feature Register 0 Here is [27:24] bits - Performance monitor model, zero - lack of PMU. But unfortunately, Cortex-A8 have no such bits, but have CCNT reg. :) WBW -- Aleksandr Rybalko