From owner-freebsd-hackers Tue Aug 29 20:04:18 1995 Return-Path: hackers-owner Received: (from majordom@localhost) by freefall.FreeBSD.org (8.6.11/8.6.6) id UAA05227 for hackers-outgoing; Tue, 29 Aug 1995 20:04:18 -0700 Received: from gndrsh.aac.dev.com (gndrsh.aac.dev.com [198.145.92.241]) by freefall.FreeBSD.org (8.6.11/8.6.6) with ESMTP id UAA05220 for ; Tue, 29 Aug 1995 20:04:14 -0700 Received: (from rgrimes@localhost) by gndrsh.aac.dev.com (8.6.11/8.6.9) id UAA05696; Tue, 29 Aug 1995 20:02:01 -0700 From: "Rodney W. Grimes" Message-Id: <199508300302.UAA05696@gndrsh.aac.dev.com> Subject: Re: S.O.S -2.1Stable and ASUSP54TP4 To: msmith@atrad.adelaide.edu.au (Michael Smith) Date: Tue, 29 Aug 1995 20:02:01 -0700 (PDT) Cc: bde@zeta.org.au, leo@lisa.rur.com, freebsd-hackers@FreeBSD.ORG, jbryant@argus.iadfw.net, rashid@haven.ios.com In-Reply-To: <199508292336.JAA27015@genesis.atrad.adelaide.edu.au> from "Michael Smith" at Aug 30, 95 09:06:20 am X-Mailer: ELM [version 2.4 PL24] MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Content-Length: 2735 Sender: hackers-owner@FreeBSD.ORG Precedence: bulk > > Bruce Evans stands accused of saying: > > > > >And to state my reason for agreement that parity is a ``itsy-bitsy comfort'', > > >think about the fact that 80% of your memory access are going to a L2 > > >cache that has never had parity on it, yet has a same FIT rate as the > > >main memory system. Basically your more likely today to take a single > > >bit error in your cache as you are in main memory :-(. > > > > Is there anything to detect or correct errors in the registers or > > control logic? > > They're not susceptible in the same way (and static memories are much less > susceptible than dynamic memories). > > The #1 cause of single-bit errors are charged particles resulting from > radioactive decay in the chip packaging materials. (One reason why > ceramic-package memories are almost extinct). > > DRAMs, which depend on the charge on a tiny capacitor, are vulnerable > to having this charge corrupted by a small storm of such particles. > > Static memories don't use this technique, and are thus resistant to > this form of corruption. I would have agreed with this 3 years ago, but I suggest you go study some of the current technology in use. First alpha particle disturbance in DRAM is gone, it was pretty much killed 4 years ago with the advent of certain epoxy materials used to coat the die with before plastic encapsolation. At todays DRAM scales a single alpha particle is enough to destroy the charge, that is why they had to pretty much eliminate them totally. Static memories are suspetable to alpha particule disturbance, it just takes a heck of a lot more to do it, and given ceramic is out of the picture it won't occur anyway. In a cmos static memory you have to have enough disturbance to perturb the gate voltage of one side of the latch to cause a bit flip, about 10 micro rinkens will do it, but it usually sends the device into latchup at the same time :-). The more prevelent cause today in single bit errors in both DRAM and SRAM is cause by VCC noise and or ION contamination caused by moisture absorbition into plastic packages before surface mount vapor phase soldering. Current FIT per bit are in the 0.0002 to 0.0004 range, that is measure in billions of power on hours. Today MTBF in a 2MB x 16 bit DRAM subsystem is 30 to 35 years... I'd say I can live with that given that my disk is going to go belly up in 57 years anyway :-) :-) :-) Sources of information for this and more details are in many vendors data books, Mircon's 1995 has a few good tech notes about it, as does Intels memory products books. -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD