From owner-freebsd-current@FreeBSD.ORG Tue Jul 8 14:28:23 2003 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 1425B37B401 for ; Tue, 8 Jul 2003 14:28:23 -0700 (PDT) Received: from troutmask.apl.washington.edu (troutmask.apl.washington.edu [128.208.78.105]) by mx1.FreeBSD.org (Postfix) with ESMTP id 802CE43FCB for ; Tue, 8 Jul 2003 14:28:22 -0700 (PDT) (envelope-from sgk@troutmask.apl.washington.edu) Received: from troutmask.apl.washington.edu (localhost [127.0.0.1]) h68LSMsb069017; Tue, 8 Jul 2003 14:28:22 -0700 (PDT) (envelope-from sgk@troutmask.apl.washington.edu) Received: (from sgk@localhost)h68LSLM7069016; Tue, 8 Jul 2003 14:28:22 -0700 (PDT) Date: Tue, 8 Jul 2003 14:28:21 -0700 From: Steve Kargl To: Thierry Herbelot Message-ID: <20030708212821.GA68477@troutmask.apl.washington.edu> References: <200307082011.49200.thierry@herbelot.com> <200307082109.20039.thierry@herbelot.com> <20030708193053.GA68383@troutmask.apl.washington.edu> <200307082147.23042.thierry@herbelot.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <200307082147.23042.thierry@herbelot.com> User-Agent: Mutt/1.4.1i cc: current ML Subject: Re: systematic panic on an SMP machine for 5.1-Release X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Jul 2003 21:28:23 -0000 On Tue, Jul 08, 2003 at 09:47:23PM +0200, Thierry Herbelot wrote: > Le Tuesday 08 July 2003 21:30, Steve Kargl a ?crit : > > On Tue, Jul 08, 2003 at 09:09:20PM +0200, Thierry Herbelot wrote: > > > TfH > > > > > > PS : as I said, the box has a 2GB RAM, so moving around the vmcore is not > > > easy > > > > Add "options DISABLE_PSE" and "options DISABLE_PG_G" > > to your kernel configuration. Report back if you > > still have a panic. > > will do tomorrow morning > > PS : is this an indication of bug in the p-III or in the chipset ? > (ISTR these options could be used to get around unnamed errata of the p-IV) > You'll need to search the mailing list archive for vague ramblings by Terry Lambert about these option, large memory machines, and bugs in the Intel CPUi architecture. I was hoping to avoid Yet Another Terry Email (YATE) on the subject, which simply tells us how clever he is without giving any details. -- Steve