Date: Thu, 4 Mar 2010 05:23:08 +0000 (UTC) From: Neel Natu <neel@FreeBSD.org> To: cvs-src-old@freebsd.org Subject: cvs commit: src/sys/mips/include cpuinfo.h src/sys/mips/mips busdma_machdep.c cpu.c src/sys/mips/sibyte sb_machdep.c Message-ID: <201003040523.o245NXTQ067501@repoman.freebsd.org>
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neel 2010-03-04 05:23:08 UTC FreeBSD src repository Modified files: sys/mips/include cpuinfo.h sys/mips/mips busdma_machdep.c cpu.c sys/mips/sibyte sb_machdep.c Log: SVN rev 204689 on 2010-03-04 05:23:08Z by neel Add support for CPUs with cache coherent DMA. The two main changes are: - We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT requests on these CPUs. - The bus_dmamap_sync() is a no-op for these CPUs. A side-effect of this change is rename DMAMAP_COHERENT flag to DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately. Reviewed by: gonzo, imp Revision Changes Path 1.3 +3 -0 src/sys/mips/include/cpuinfo.h 1.8 +24 -9 src/sys/mips/mips/busdma_machdep.c 1.4 +1 -1 src/sys/mips/mips/cpu.c 1.7 +7 -0 src/sys/mips/sibyte/sb_machdep.c
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