From owner-svn-src-head@FreeBSD.ORG Wed Aug 18 08:22:58 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id B675F1065674; Wed, 18 Aug 2010 08:22:58 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id A6BA48FC15; Wed, 18 Aug 2010 08:22:58 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o7I8MwoM059617; Wed, 18 Aug 2010 08:22:58 GMT (envelope-from adrian@svn.freebsd.org) Received: (from adrian@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o7I8MwqQ059615; Wed, 18 Aug 2010 08:22:58 GMT (envelope-from adrian@svn.freebsd.org) Message-Id: <201008180822.o7I8MwqQ059615@svn.freebsd.org> From: Adrian Chadd Date: Wed, 18 Aug 2010 08:22:58 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r211448 - head/sys/mips/atheros X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 18 Aug 2010 08:22:58 -0000 Author: adrian Date: Wed Aug 18 08:22:58 2010 New Revision: 211448 URL: http://svn.freebsd.org/changeset/base/211448 Log: Add a further register definition for USB device initialisation. Obtained from: Linux Modified: head/sys/mips/atheros/ar91xxreg.h Modified: head/sys/mips/atheros/ar91xxreg.h ============================================================================== --- head/sys/mips/atheros/ar91xxreg.h Wed Aug 18 08:22:09 2010 (r211447) +++ head/sys/mips/atheros/ar91xxreg.h Wed Aug 18 08:22:58 2010 (r211448) @@ -34,6 +34,8 @@ /* reset block */ #define AR91XX_RESET_REG_RESET_MODULE AR71XX_RST_BLOCK_BASE + 0x1c +#define AR91XX_RST_RESET_MODULE_USBSUS_OVERRIDE (1 << 10) + /* PLL block */ #define AR91XX_PLL_REG_CPU_CONFIG AR71XX_PLL_CPU_BASE + 0x00 #define AR91XX_PLL_REG_ETH_CONFIG AR71XX_PLL_CPU_BASE + 0x04