From owner-svn-src-head@FreeBSD.ORG Sun Apr 5 05:14:22 2015 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id D277D66C; Sun, 5 Apr 2015 05:14:22 +0000 (UTC) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id B55D39DC; Sun, 5 Apr 2015 05:14:22 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.9/8.14.9) with ESMTP id t355EMH2001257; Sun, 5 Apr 2015 05:14:22 GMT (envelope-from rpaulo@FreeBSD.org) Received: (from rpaulo@localhost) by svn.freebsd.org (8.14.9/8.14.9/Submit) id t355ELbP001250; Sun, 5 Apr 2015 05:14:21 GMT (envelope-from rpaulo@FreeBSD.org) Message-Id: <201504050514.t355ELbP001250@svn.freebsd.org> X-Authentication-Warning: svn.freebsd.org: rpaulo set sender to rpaulo@FreeBSD.org using -f From: Rui Paulo Date: Sun, 5 Apr 2015 05:14:21 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r281102 - in head/sys: dev/hwpmc sys X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.18-1 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 05 Apr 2015 05:14:22 -0000 Author: rpaulo Date: Sun Apr 5 05:14:20 2015 New Revision: 281102 URL: https://svnweb.freebsd.org/changeset/base/281102 Log: hwpmc: add initial Intel Broadwell support. The full list of aliases and events will follow in a subsequent commit. MFC after: 1 month Modified: head/sys/dev/hwpmc/hwpmc_core.c head/sys/dev/hwpmc/hwpmc_intel.c head/sys/dev/hwpmc/pmc_events.h head/sys/sys/pmc.h Modified: head/sys/dev/hwpmc/hwpmc_core.c ============================================================================== --- head/sys/dev/hwpmc/hwpmc_core.c Sun Apr 5 05:09:38 2015 (r281101) +++ head/sys/dev/hwpmc/hwpmc_core.c Sun Apr 5 05:14:20 2015 (r281102) @@ -574,7 +574,8 @@ struct iap_event_descr { #define IAP_F_HW (1 << 10) /* CPU: Haswell */ #define IAP_F_CAS (1 << 11) /* CPU: Atom Silvermont */ #define IAP_F_HWX (1 << 12) /* CPU: Haswell Xeon */ -#define IAP_F_FM (1 << 13) /* Fixed mask */ +#define IAP_F_BW (1 << 13) /* CPU: Broadwell */ +#define IAP_F_FM (1 << 14) /* Fixed mask */ #define IAP_F_ALLCPUSCORE2 \ (IAP_F_CC | IAP_F_CC2 | IAP_F_CC2E | IAP_F_CA) @@ -2074,6 +2075,7 @@ iap_allocate_pmc(int cpu, int ri, struct if (iap_event_corei7_ok_on_counter(ev, ri) == 0) return (EINVAL); break; + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_SANDYBRIDGE_XEON: case PMC_CPU_INTEL_IVYBRIDGE: @@ -2106,6 +2108,9 @@ iap_allocate_pmc(int cpu, int ri, struct case PMC_CPU_INTEL_ATOM_SILVERMONT: cpuflag = IAP_F_CAS; break; + case PMC_CPU_INTEL_BROADWELL: + cpuflag = IAP_F_BW; + break; case PMC_CPU_INTEL_CORE: cpuflag = IAP_F_CC; break; Modified: head/sys/dev/hwpmc/hwpmc_intel.c ============================================================================== --- head/sys/dev/hwpmc/hwpmc_intel.c Sun Apr 5 05:09:38 2015 (r281101) +++ head/sys/dev/hwpmc/hwpmc_intel.c Sun Apr 5 05:14:20 2015 (r281102) @@ -179,6 +179,10 @@ pmc_intel_initialize(void) cputype = PMC_CPU_INTEL_IVYBRIDGE_XEON; nclasses = 3; break; + case 0x3D: + cputype = PMC_CPU_INTEL_BROADWELL; + nclasses = 3; + break; case 0x3F: /* Per Intel document 325462-045US 09/2014. */ case 0x46: /* Per Intel document 325462-045US 09/2014. */ /* Should 46 be XEON. probably its own? */ @@ -227,6 +231,7 @@ pmc_intel_initialize(void) */ case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_ATOM_SILVERMONT: + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: @@ -295,6 +300,7 @@ pmc_intel_initialize(void) case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: case PMC_CPU_INTEL_WESTMERE: + case PMC_CPU_INTEL_BROADWELL: error = pmc_uncore_initialize(pmc_mdep, ncpus); break; default: @@ -319,6 +325,7 @@ pmc_intel_finalize(struct pmc_mdep *md) #if defined(__i386__) || defined(__amd64__) case PMC_CPU_INTEL_ATOM: case PMC_CPU_INTEL_ATOM_SILVERMONT: + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_CORE: case PMC_CPU_INTEL_CORE2: case PMC_CPU_INTEL_CORE2EXTREME: @@ -360,6 +367,7 @@ pmc_intel_finalize(struct pmc_mdep *md) */ #if defined(__i386__) || defined(__amd64__) switch (md->pmd_cputype) { + case PMC_CPU_INTEL_BROADWELL: case PMC_CPU_INTEL_COREI7: case PMC_CPU_INTEL_HASWELL: case PMC_CPU_INTEL_SANDYBRIDGE: Modified: head/sys/dev/hwpmc/pmc_events.h ============================================================================== --- head/sys/dev/hwpmc/pmc_events.h Sun Apr 5 05:09:38 2015 (r281101) +++ head/sys/dev/hwpmc/pmc_events.h Sun Apr 5 05:14:20 2015 (r281102) @@ -1554,6 +1554,11 @@ __PMC_EV_ALIAS("BACLEARS.RETURN", I __PMC_EV_ALIAS("BACLEARS.COND", IAP_EVENT_E6H_10H) \ __PMC_EV_ALIAS("MS_DECODED.MS_ENTRY", IAP_EVENT_E7H_01H) +/* + * Aliases for Broadwell PMC events. + */ +#define __PMC_EV_ALIAS_BROADWELL() \ +__PMC_EV_ALIAS_INTEL_ARCHITECTURAL() /* * Aliases for Core PMC events. @@ -4228,6 +4233,11 @@ __PMC_EV(UCP, EVENT_86H_01H) #define PMC_EV_UCP_FIRST PMC_EV_UCP_EVENT_00H_01H #define PMC_EV_UCP_LAST PMC_EV_UCP_EVENT_86H_01H +/* + * Aliases for Broadwell uncore PMC events + */ +#define __PMC_EV_ALIAS_BROADWELLUC() + #define __PMC_EV_ALIAS_COREI7UC() \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.READ_TRACKER", UCP_EVENT_00H_01H) \ __PMC_EV_ALIAS("GQ_CYCLES_FULL.WRITE_TRACKER", UCP_EVENT_00H_02H) \ Modified: head/sys/sys/pmc.h ============================================================================== --- head/sys/sys/pmc.h Sun Apr 5 05:09:38 2015 (r281101) +++ head/sys/sys/pmc.h Sun Apr 5 05:14:20 2015 (r281102) @@ -96,6 +96,7 @@ __PMC_CPU(INTEL_NEHALEM_EX, 0x93, "Intel Nehalem Xeon 7500") \ __PMC_CPU(INTEL_WESTMERE_EX, 0x94, "Intel Westmere Xeon E7") \ __PMC_CPU(INTEL_HASWELL_XEON, 0x95, "Intel Haswell Xeon E5 v3") \ + __PMC_CPU(INTEL_BROADWELL, 0x96, "Intel Broadwell") \ __PMC_CPU(INTEL_XSCALE, 0x100, "Intel XScale") \ __PMC_CPU(MIPS_24K, 0x200, "MIPS 24K") \ __PMC_CPU(MIPS_OCTEON, 0x201, "Cavium Octeon") \