From owner-freebsd-mips@FreeBSD.ORG  Sat Oct  5 23:07:16 2013
Return-Path: <owner-freebsd-mips@FreeBSD.ORG>
Delivered-To: freebsd-mips@freebsd.org
Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115])
 (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits))
 (No client certificate requested)
 by hub.freebsd.org (Postfix) with ESMTP id D7BE2C50;
 Sat,  5 Oct 2013 23:07:16 +0000 (UTC)
 (envelope-from stas@FreeBSD.org)
Received: from mx0.deglitch.com (backbone.deglitch.com [78.110.53.255])
 by mx1.freebsd.org (Postfix) with ESMTP id 907A02A64;
 Sat,  5 Oct 2013 23:07:16 +0000 (UTC)
Received: from [192.168.11.3] (c-71-198-23-5.hsd1.ca.comcast.net [71.198.23.5])
 by mx0.deglitch.com (Postfix) with ESMTPSA id 5D1D08FC2B;
 Sun,  6 Oct 2013 03:07:02 +0400 (MSK)
References: <CAJ-Vmo=PNSsW0eEAhc9LEDLswsj41VN+FX1vakQL=qGGdKqMuw@mail.gmail.com>
Mime-Version: 1.0 (1.0)
In-Reply-To: <CAJ-Vmo=PNSsW0eEAhc9LEDLswsj41VN+FX1vakQL=qGGdKqMuw@mail.gmail.com>
Content-Type: text/plain;
	charset=us-ascii
Content-Transfer-Encoding: quoted-printable
Message-Id: <5AD9EE93-9D19-4A07-B189-43DA0C4A85E9@FreeBSD.org>
X-Mailer: iPad Mail (10B329)
From: Stanislav Sedov <stas@FreeBSD.org>
Subject: Re: How's bus-space stuff supposed to work with superscalar MIPS?
Date: Sat, 5 Oct 2013 16:06:58 -0700
To: Adrian Chadd <adrian@freebsd.org>
Cc: "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org>
X-BeenThere: freebsd-mips@freebsd.org
X-Mailman-Version: 2.1.14
Precedence: list
List-Id: Porting FreeBSD to MIPS <freebsd-mips.freebsd.org>
List-Unsubscribe: <http://lists.freebsd.org/mailman/options/freebsd-mips>,
 <mailto:freebsd-mips-request@freebsd.org?subject=unsubscribe>
List-Archive: <http://lists.freebsd.org/pipermail/freebsd-mips>
List-Post: <mailto:freebsd-mips@freebsd.org>
List-Help: <mailto:freebsd-mips-request@freebsd.org?subject=help>
List-Subscribe: <http://lists.freebsd.org/mailman/listinfo/freebsd-mips>,
 <mailto:freebsd-mips-request@freebsd.org?subject=subscribe>
X-List-Received-Date: Sat, 05 Oct 2013 23:07:16 -0000


On Oct 5, 2013, at 10:18 AM, Adrian Chadd <adrian@freebsd.org> wrote:

> Hi all,
>=20
> I've been bringing up the AR9344 PHY and after a lot of digging, I
> discovered that I can fix things by changing ARGE_WRITE() (ie, write to th=
e
> ethernet space registers) to:
>=20
> bus_write_4();
> bus_read_4();
>=20
> .. to (what I'm guessing here) flush the write out before the next
> instruction is run.
>=20
> So, given this particular hilarity has shown up, what's the story with
> doing IO accesses on a superscalar MIPS CPU? If it's going to kseg1, is it=

> somehow going to magically enforce ordering? Or am I right in thinking we
> will need explicit barriers here?
>=20

I don't know specifics of mips74k, but usually one indeed needs memory barri=
ers
when performing read of write operation sequences that require ordering on
device I/O (e.g changing the ring and writing the new ring index afterwards)=
.  I would
not be surprised if the cpu reorders i/o bus memory access, especially a mul=
ti-issue
one.

It is a good idea to have barriers where needed regardless.  We have special=
 macros
for them which are defined to nothing on the in-order platforms.=