From owner-freebsd-stable@FreeBSD.ORG Wed Jul 21 09:17:17 2010 Return-Path: Delivered-To: freebsd-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A18BD1065675; Wed, 21 Jul 2010 09:17:17 +0000 (UTC) (envelope-from avg@icyb.net.ua) Received: from citadel.icyb.net.ua (citadel.icyb.net.ua [212.40.38.140]) by mx1.freebsd.org (Postfix) with ESMTP id AF3F28FC2E; Wed, 21 Jul 2010 09:17:16 +0000 (UTC) Received: from porto.topspin.kiev.ua (porto-e.starpoint.kiev.ua [212.40.38.100]) by citadel.icyb.net.ua (8.8.8p3/ICyb-2.3exp) with ESMTP id MAA23801; Wed, 21 Jul 2010 12:17:07 +0300 (EEST) (envelope-from avg@icyb.net.ua) Received: from localhost.topspin.kiev.ua ([127.0.0.1]) by porto.topspin.kiev.ua with esmtp (Exim 4.34 (FreeBSD)) id 1ObVQJ-000Ngi-2u; Wed, 21 Jul 2010 12:17:07 +0300 Message-ID: <4C46BB12.6090903@icyb.net.ua> Date: Wed, 21 Jul 2010 12:17:06 +0300 From: Andriy Gapon User-Agent: Thunderbird 2.0.0.24 (X11/20100603) MIME-Version: 1.0 To: Markus Gebert References: <6B57591F-9FA2-45EB-825F-1DB025C0635D@hostpoint.ch> <9DCFE2F6-D7CB-49CB-8EBC-06C1E5EBB727@hostpoint.ch> <201007201559.45081.jhb@freebsd.org> <6781BC8B-51E0-4F8B-9307-9C062DE70C21@hostpoint.ch> <4C46B0C6.4020400@icyb.net.ua> In-Reply-To: <4C46B0C6.4020400@icyb.net.ua> X-Enigmail-Version: 0.96.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: freebsd-stable@freebsd.org, John Baldwin Subject: Re: 8.1-RC2 MCE caused by some LAPIC/clock changes? X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 21 Jul 2010 09:17:17 -0000 on 21/07/2010 11:33 Andriy Gapon said the following: > Not sure how to interpret this properly. > One possibility is a hardware problem where interrupt message route between > ioapic2 and CPU to which lapic3 belongs is flaky. Or, I/O path between that CPU and the PCI slot where the device resides. Or the CPU. Or... I think that lapic2 and lapic3 reside in a different physical package/socket, given that you have 2x2 CPU/core configuration. BTW, John, could there be any problem because of this: ioapic1: WARNING: intbase 48 != expected base 24 ioapic2: WARNING: intbase 56 != expected base 55 ioapic3: WARNING: intbase 24 != expected base 63 -- Andriy Gapon