Date: Tue, 19 Nov 1996 15:47:09 -0700 From: Steve Passe <smp@csn.net> To: smp@freebsd.org Subject: Re: Can test again... Message-ID: <199611192247.PAA20421@clem.systemsix.com> In-Reply-To: Your message of "Tue, 19 Nov 1996 13:55:50 MST." <199611192055.NAA19886@clem.systemsix.com>
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Hi, >I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID INT# > INT active-lo level 1 9 2 17 > ^ ^ ^^ > ... >Is there anything in the BIOS that looks like it might affect this behavior? > ... >So, its debate time, is this MP declaration that Asus is using on >its P/I-P65UP5/C-P6ND motherboard correct? I checked the database >and they DO NOT do this on either the P54NP4 or P55P2T4D (both EISA/PCI). >I'm going back to re-read the spec to see if I can find this variation. >If its legal I'll redo the code to make it work. If it's bogus I'll >have to add some sort of "rogue hardware" patch that is enabled with >a kernel config option. Tor Egge just reported: >I found an MPS 1.4 support switch in bios, it was disabled. Changing >it to enabled caused some changes. New version of mptable -dmesg -verbose >is appended. SMP kernel with option APIC_IO now boots fine. Perhaps >this version should replace the previous version in the mptable output >database. > ... > INT active-lo level 0 11:A 2 17 > INT active-lo level 0 12:A 2 16 --- So I guess its a moot point for now. I did check out the MP spec, ver1.1, and it does have section D.3 (I/O Interrupt Assignment Entries for PCI Devices) It appears identical to the D.3 section of ver1.4, so this doesn't explain why Asus did it this way. Perhaps ver1.1 was originally published without appendix D? Oh well, on to other problems.... -- Steve Passe | powered by smp@csn.net | FreeBSD
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