Date: Mon, 22 Apr 2024 18:06:24 +0000 From: bugzilla-noreply@freebsd.org To: virtualization@FreeBSD.org Subject: [Bug 278448] Linux emulation not working same as bhyve instance Message-ID: <bug-278448-27103-Mh9x25bAug@https.bugs.freebsd.org/bugzilla/> In-Reply-To: <bug-278448-27103@https.bugs.freebsd.org/bugzilla/> References: <bug-278448-27103@https.bugs.freebsd.org/bugzilla/>
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https://bugs.freebsd.org/bugzilla/show_bug.cgi?id=3D278448 --- Comment #3 from crb <crb@ChrisBowman.com> --- I've used a read_verilog/add_files/import_files (I've tried them all) to re= ad in a file. Vivado, in the GUI (there is no error from the tcl shel) lists these as non-module files. And when I try to instanciate one of the modules into a board design that module isn't available. My speculation is that vi= vado forks a process to read the module, that crashes and returns a failure and = so Vivado has no further information other than it isn't verilog. I have no reason to believe this it's just speculation. As I said I have the exact same script and same files from the same NFS ser= ver running under Linux/bhyve and it works as expected. # import_files -fileset sources_1 -norecurse {../source/verilog/mm_axi_ssd.v ../source/verilog/mm_axi_ssd_core.v} # update_compile_order -fileset sources_1 CRITICAL WARNING: [filemgmt 20-730] Could not find a top module in the file= set sources_1. Resolution: With the gui up, review the source files in the Sources window.= Use Add Sources to add any needed sources. If the files are disabled, enable th= em. You can also select the file and choose Set Used In from the pop-up menu. Review if they are being used at the proper points of the flow. # create_bd_design "axi_ssd_top" Wrote : </homes/crb/Arty_Z7/article_projects/axi_mm_ssd/hardware/implementation/my_= project/my_project.srcs/sources_1/bd/axi_ssd_top/axi_ssd_top.bd>=20 # create_root_design "" ERROR: [filemgmt 56-587] Failed to resolve reference. Nothing was found in = the project to match the name mm_axi_ssd Try changing the compile order from ma= nual to automatic.=20 ERROR: [BD 41-1690] Unable to resolve module-source based on inputs: mm_axi= _ssd ERROR: [BD 5-7] Error: running create_bd_cell -type module -reference mm_axi_ssd -name mm_axi_ssd_inst . ERROR: [Common 17-39] 'create_bd_cell' failed due to earlier errors. while executing "create_bd_cell -type module -reference mm_axi_ssd mm_axi_ssd_inst " (procedure "create_root_design" line 42) invoked from within "create_root_design """ (file "../scripts/project.tcl" line 150) --=20 You are receiving this mail because: You are the assignee for the bug.=
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