From owner-freebsd-current Wed Sep 1 20:44:38 1999 Delivered-To: freebsd-current@freebsd.org Received: from khavrinen.lcs.mit.edu (khavrinen.lcs.mit.edu [18.24.4.193]) by hub.freebsd.org (Postfix) with ESMTP id 002E014FDA for ; Wed, 1 Sep 1999 20:44:34 -0700 (PDT) (envelope-from wollman@khavrinen.lcs.mit.edu) Received: (from wollman@localhost) by khavrinen.lcs.mit.edu (8.9.1/8.9.1) id XAA08465; Wed, 1 Sep 1999 23:43:12 -0400 (EDT) (envelope-from wollman) Date: Wed, 1 Sep 1999 23:43:12 -0400 (EDT) From: Garrett Wollman Message-Id: <199909020343.XAA08465@khavrinen.lcs.mit.edu> To: Warner Losh Cc: freebsd-current@FreeBSD.ORG Subject: Re: followup to apm problems. In-Reply-To: <199909012247.QAA20600@harmony.village.org> References: <199909011345.JAA05781@khavrinen.lcs.mit.edu> <199908312120.PAA13660@harmony.village.org> <199908312216.PAA00882@dingo.cdrom.com> <199909012247.QAA20600@harmony.village.org> Sender: owner-freebsd-current@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.ORG < said: [I wrote:] > : And designs based on the Intel PIIX4 will generate SMI# interrupts for > : whichever activities are programmed in the BIOS, completely bypassing > : the traditional interrupt mechanism. > So does that mean if we do disable them at the PIC level we'll be OK? No, it means if you disable [interrupts] at the PIC level it will have no effect on whether or not the system resumes immediately, since they don't go through the PIC to get to the BIOS. -GAWollman -- Garrett A. Wollman | O Siem / We are all family / O Siem / We're all the same wollman@lcs.mit.edu | O Siem / The fires of freedom Opinions not those of| Dance in the burning flame MIT, LCS, CRS, or NSA| - Susan Aglukark and Chad Irschick To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-current" in the body of the message