From owner-svn-src-head@FreeBSD.ORG Wed Jun 23 23:16:27 2010 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AD99A1065672; Wed, 23 Jun 2010 23:16:27 +0000 (UTC) (envelope-from marcel@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 9CC618FC13; Wed, 23 Jun 2010 23:16:27 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o5NNGRDg009614; Wed, 23 Jun 2010 23:16:27 GMT (envelope-from marcel@svn.freebsd.org) Received: (from marcel@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o5NNGRNx009612; Wed, 23 Jun 2010 23:16:27 GMT (envelope-from marcel@svn.freebsd.org) Message-Id: <201006232316.o5NNGRNx009612@svn.freebsd.org> From: Marcel Moolenaar Date: Wed, 23 Jun 2010 23:16:27 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r209489 - head/sys/powerpc/mpc85xx X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Jun 2010 23:16:27 -0000 Author: marcel Date: Wed Jun 23 23:16:27 2010 New Revision: 209489 URL: http://svn.freebsd.org/changeset/base/209489 Log: With openpic(4) using active-low as the default polarity, reconfigure the internal interrupt sources as active-high. The internal interrupt sources are disabled when programmed as active-low. Note that the internal interrupts have no sense bit like the external interrupts. We program them as edge-triggered to make sure we write a 0 value to a reserved register. It does not in any way say anything about the sense of internal interrupt. Modified: head/sys/powerpc/mpc85xx/ocpbus.c Modified: head/sys/powerpc/mpc85xx/ocpbus.c ============================================================================== --- head/sys/powerpc/mpc85xx/ocpbus.c Wed Jun 23 23:07:57 2010 (r209488) +++ head/sys/powerpc/mpc85xx/ocpbus.c Wed Jun 23 23:16:27 2010 (r209489) @@ -277,8 +277,15 @@ ocpbus_attach(device_t dev) ccsr_read4(OCP85XX_PORDEVSR), ccsr_read4(OCP85XX_PORDEVSR2)); - for (i = INTR_VEC(OPIC_ID, 0); i < INTR_VEC(OPIC_ID, 4); i++) - powerpc_config_intr(i, INTR_TRIGGER_LEVEL, INTR_POLARITY_LOW); + /* + * Internal interrupt are always active-high. Since the sense cannot + * be specified, we program as edge-triggered to make sure we write + * a 0 value to the reserved bit in the OpenPIC compliant PIC. This + * is not to say anything about the sense of any of the internal + * interrupt sources. + */ + for (i = PIC_IRQ_INT(0); i < PIC_IRQ_INT(32); i++) + powerpc_config_intr(i, INTR_TRIGGER_EDGE, INTR_POLARITY_HIGH); return (bus_generic_attach(dev)); }