Date: Sat, 23 May 2020 19:04:30 +0000 (UTC) From: Yuri Victorovich <yuri@FreeBSD.org> To: ports-committers@freebsd.org, svn-ports-all@freebsd.org, svn-ports-head@freebsd.org Subject: svn commit: r536332 - head/cad/verilator Message-ID: <202005231904.04NJ4UfZ090664@repo.freebsd.org>
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Author: yuri Date: Sat May 23 19:04:30 2020 New Revision: 536332 URL: https://svnweb.freebsd.org/changeset/ports/536332 Log: cad/verilator: Update 4.028 -> 4.034 PR: 243698 Approved by: kevinz5000@gmail.com (maintainer's timeout; 110 days) Modified: head/cad/verilator/Makefile head/cad/verilator/distinfo head/cad/verilator/pkg-plist Modified: head/cad/verilator/Makefile ============================================================================== --- head/cad/verilator/Makefile Sat May 23 19:01:25 2020 (r536331) +++ head/cad/verilator/Makefile Sat May 23 19:04:30 2020 (r536332) @@ -1,9 +1,12 @@ # $FreeBSD$ PORTNAME= verilator -DISTVERSION= 4.028 +DISTVERSION= 4.034 CATEGORIES= cad MASTER_SITES= https://www.veripool.org/ftp/ + +PATCH_SITES= https://github.com/${PORTNAME}/${PORTNAME}/commit/ +PATCHFILES+= 39f16fb155b9e909f919a9d4ae06890395987b16.patch:-p1 # https://github.com/verilator/verilator/pull/2353 MAINTAINER= kevinz5000@gmail.com COMMENT= Synthesizable Verilog to C++ compiler Modified: head/cad/verilator/distinfo ============================================================================== --- head/cad/verilator/distinfo Sat May 23 19:01:25 2020 (r536331) +++ head/cad/verilator/distinfo Sat May 23 19:04:30 2020 (r536332) @@ -1,3 +1,5 @@ -TIMESTAMP = 1581485426 -SHA256 (verilator-4.028.tgz) = 344c859b105eb4d382ab89fbc515fd3bf915dc17bf75f90e918141afac1489e6 -SIZE (verilator-4.028.tgz) = 2448209 +TIMESTAMP = 1590260103 +SHA256 (verilator-4.034.tgz) = 54ed7b06ee28b5d21f9d0ee98406d29a508e6124b0d10e54bb32081613ddb80b +SIZE (verilator-4.034.tgz) = 2612571 +SHA256 (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = e0b01464624bd340c2969c47e7c851e9cacf7e25281df3bf9b9b0da2eea33582 +SIZE (39f16fb155b9e909f919a9d4ae06890395987b16.patch) = 588 Modified: head/cad/verilator/pkg-plist ============================================================================== --- head/cad/verilator/pkg-plist Sat May 23 19:01:25 2020 (r536331) +++ head/cad/verilator/pkg-plist Sat May 23 19:04:30 2020 (r536332) @@ -41,6 +41,9 @@ man/man1/verilator_profcfunc.1.gz %%DATADIR%%/examples/make_tracing_sc/sc_main.cpp %%DATADIR%%/examples/make_tracing_sc/sub.v %%DATADIR%%/examples/make_tracing_sc/top.v +%%DATADIR%%/examples/xml_py/Makefile +%%DATADIR%%/examples/xml_py/sub.v +%%DATADIR%%/examples/xml_py/top.v %%DATADIR%%/include/gtkwave/fastlz.c %%DATADIR%%/include/gtkwave/fastlz.h %%DATADIR%%/include/gtkwave/fst_config.h @@ -64,6 +67,7 @@ man/man1/verilator_profcfunc.1.gz %%DATADIR%%/include/verilated_fst_c.h %%DATADIR%%/include/verilated_heavy.h %%DATADIR%%/include/verilated_imp.h +%%DATADIR%%/include/verilated_intrinsics.h %%DATADIR%%/include/verilated_save.cpp %%DATADIR%%/include/verilated_save.h %%DATADIR%%/include/verilated_sc.h @@ -71,6 +75,8 @@ man/man1/verilator_profcfunc.1.gz %%DATADIR%%/include/verilated_syms.h %%DATADIR%%/include/verilated_threads.cpp %%DATADIR%%/include/verilated_threads.h +%%DATADIR%%/include/verilated_trace.h +%%DATADIR%%/include/verilated_trace_imp.cpp %%DATADIR%%/include/verilated_unordered_set_map.h %%DATADIR%%/include/verilated_vcd_c.cpp %%DATADIR%%/include/verilated_vcd_c.h
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