Date: Wed, 2 May 2001 12:06:08 +1000 From: "Andrew Reilly" <areilly@bigpond.net.au> To: Graywane <graywane@home.com> Cc: stable@FreeBSD.ORG Subject: Re: Trouble with 4.3-RELEASE compiler Message-ID: <20010502120608.E1059@gurney.reilly.home> In-Reply-To: <20010427210644.A1197@home.com>; from graywane@home.com on Fri, Apr 27, 2001 at 09:06:45PM -0400 References: <20010427155725.L18676@fw.wintelcom.net> <200104280035.UAA11427@ns1.rwwa.com> <20010427210644.A1197@home.com>
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On Fri, Apr 27, 2001 at 09:06:45PM -0400, Graywane wrote: > the program that demonstrates the problem. The problem is that it is hard to > code a strength reduce optimization on platforms with small register sets > (such as the Intel platform). Having very few people truly understand the > optimization code while trying to support numerous platforms only > exacerbates the problem. I haven't ever looked at the innards of gcc. I'm surprised that this is a register allocation issue, as I would have expected that strength reduction (and inline) manipulations would be performed at the target-independant, parse-tree level, before instruction selection and register allocation had even been done. I've even seen a TI DSP C compiler that had a flag that allowed you to emit the result of most of the optimisation operations as an equivelant C file. Oh well. Gcc is what we've got. Might as well learn to live with it. -- Andrew To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-stable" in the body of the message
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