Skip site navigation (1)Skip section navigation (2)
Date:      Wed, 22 Oct 2008 00:01:53 +0000 (UTC)
From:      Jung-uk Kim <jkim@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r184146 - in head/sys: amd64/amd64 amd64/include i386/i386 i386/include
Message-ID:  <200810220001.m9M01rLq011948@svn.freebsd.org>

next in thread | raw e-mail | index | archive | help
Author: jkim
Date: Wed Oct 22 00:01:53 2008
New Revision: 184146
URL: http://svn.freebsd.org/changeset/base/184146

Log:
  Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher
  even if BIOS does not advertise it.

Modified:
  head/sys/amd64/amd64/identcpu.c
  head/sys/amd64/include/specialreg.h
  head/sys/i386/i386/identcpu.c
  head/sys/i386/include/specialreg.h

Modified: head/sys/amd64/amd64/identcpu.c
==============================================================================
--- head/sys/amd64/amd64/identcpu.c	Tue Oct 21 23:36:28 2008	(r184145)
+++ head/sys/amd64/amd64/identcpu.c	Wed Oct 22 00:01:53 2008	(r184146)
@@ -348,7 +348,9 @@ printcpuinfo(void)
 				cpu_feature &= ~CPUID_HTT;
 
 			if (!tsc_is_invariant &&
-			    (amd_pminfo & AMDPM_TSC_INVARIANT)) {
+			    (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
+			    ((amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
+			    AMD64_CPU_FAMILY(cpu_id) >= 0x10))) {
 				tsc_is_invariant = 1;
 				printf("\n  P-state invariant TSC");
 			}

Modified: head/sys/amd64/include/specialreg.h
==============================================================================
--- head/sys/amd64/include/specialreg.h	Tue Oct 21 23:36:28 2008	(r184145)
+++ head/sys/amd64/include/specialreg.h	Wed Oct 22 00:01:53 2008	(r184146)
@@ -153,6 +153,23 @@
 #define	AMDID2_PREFETCH	0x00000100
 
 /*
+ * CPUID instruction 1 eax info
+ */
+#define	CPUID_STEPPING		0x0000000f
+#define	CPUID_MODEL		0x000000f0
+#define	CPUID_FAMILY		0x00000f00
+#define	CPUID_EXT_MODEL		0x000f0000
+#define	CPUID_EXT_FAMILY	0x0ff00000
+#define	AMD64_CPU_MODEL(id) \
+    ((((id) & CPUID_MODEL) >> 4) | \
+    ((((id) & CPUID_FAMILY) >= 0x600) ? \
+    (((id) & CPUID_EXT_MODEL) >> 12) : 0))
+#define	AMD64_CPU_FAMILY(id) \
+    ((((id) & CPUID_FAMILY) >> 8) + \
+    ((((id) & CPUID_FAMILY) == 0xf00) ? \
+    (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
+
+/*
  * CPUID instruction 1 ebx info
  */
 #define	CPUID_BRAND_INDEX	0x000000ff

Modified: head/sys/i386/i386/identcpu.c
==============================================================================
--- head/sys/i386/i386/identcpu.c	Tue Oct 21 23:36:28 2008	(r184145)
+++ head/sys/i386/i386/identcpu.c	Wed Oct 22 00:01:53 2008	(r184146)
@@ -842,7 +842,9 @@ printcpuinfo(void)
 				cpu_feature &= ~CPUID_HTT;
 
 			if (!tsc_is_invariant &&
-			    (amd_pminfo & AMDPM_TSC_INVARIANT)) {
+			    (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
+			    (amd_pminfo & AMDPM_TSC_INVARIANT) != 0 ||
+			    I386_CPU_FAMILY(cpu_id) >= 0x10))) {
 				tsc_is_invariant = 1;
 				printf("\n  P-state invariant TSC");
 			}

Modified: head/sys/i386/include/specialreg.h
==============================================================================
--- head/sys/i386/include/specialreg.h	Tue Oct 21 23:36:28 2008	(r184145)
+++ head/sys/i386/include/specialreg.h	Wed Oct 22 00:01:53 2008	(r184146)
@@ -150,6 +150,23 @@
 #define	AMDID2_PREFETCH	0x00000100
 
 /*
+ * CPUID instruction 1 eax info
+ */
+#define	CPUID_STEPPING		0x0000000f
+#define	CPUID_MODEL		0x000000f0
+#define	CPUID_FAMILY		0x00000f00
+#define	CPUID_EXT_MODEL		0x000f0000
+#define	CPUID_EXT_FAMILY	0x0ff00000
+#define	I386_CPU_MODEL(id) \
+    ((((id) & CPUID_MODEL) >> 4) | \
+    ((((id) & CPUID_FAMILY) >= 0x600) ? \
+    (((id) & CPUID_EXT_MODEL) >> 12) : 0))
+#define	I386_CPU_FAMILY(id) \
+    ((((id) & CPUID_FAMILY) >> 8) + \
+    ((((id) & CPUID_FAMILY) == 0xf00) ? \
+    (((id) & CPUID_EXT_FAMILY) >> 20) : 0))
+
+/*
  * CPUID instruction 1 ebx info
  */
 #define	CPUID_BRAND_INDEX	0x000000ff



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?200810220001.m9M01rLq011948>