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[209.85.128.178]) by smtp.gmail.com with ESMTPSA id 00721157ae682-6e2d927f569sm7577307b3.50.2024.10.06.12.21.09 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 06 Oct 2024 12:21:10 -0700 (PDT) Received: by mail-yw1-f178.google.com with SMTP id 00721157ae682-6d6891012d5so30115807b3.2 for ; Sun, 06 Oct 2024 12:21:09 -0700 (PDT) X-Received: by 2002:a05:690c:2e90:b0:6dd:ba22:d946 with SMTP id 00721157ae682-6e2c7017d04mr62330537b3.13.1728242468860; Sun, 06 Oct 2024 12:21:08 -0700 (PDT) List-Id: FreeBSD on the RISC-V instruction set architecture List-Archive: https://lists.freebsd.org/archives/freebsd-riscv List-Help: List-Post: List-Subscribe: List-Unsubscribe: X-BeenThere: freebsd-riscv@freebsd.org Sender: owner-freebsd-riscv@FreeBSD.org MIME-Version: 1.0 References: In-Reply-To: From: Tomek CEDRO Date: Sun, 6 Oct 2024 21:20:57 +0200 X-Gmail-Original-Message-ID: Message-ID: Subject: Fwd: Soft RISC-V Systems Workshop - Call for Participation and Proposals To: "freebsd-riscv@FreeBSD.org" Content-Type: multipart/alternative; boundary="0000000000007144360623d3ce26" X-Spamd-Result: default: False [-3.30 / 15.00]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-0.999]; R_DKIM_ALLOW(-0.20)[cedro.info:s=google]; MIME_GOOD(-0.10)[multipart/alternative,text/plain]; RCPT_COUNT_ONE(0.00)[1]; RCVD_VIA_SMTP_AUTH(0.00)[]; ASN(0.00)[asn:15169, ipnet:2607:f8b0::/32, country:US]; MISSING_XM_UA(0.00)[]; MIME_TRACE(0.00)[0:+,1:+,2:~]; REDIRECTOR_URL(0.00)[sendgrid.net]; ARC_NA(0.00)[]; REDIRECTOR_FALSE(0.00)[google.com->sendgrid.net:sendgrid.net,riscv.org->sendgrid.net:sendgrid.net,forms.gle->sendgrid.net:sendgrid.net]; R_SPF_NA(0.00)[no SPF record]; DMARC_NA(0.00)[cedro.info]; MLMMJ_DEST(0.00)[freebsd-riscv@freebsd.org]; TO_DN_EQ_ADDR_ALL(0.00)[]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; RCVD_IN_DNSWL_NONE(0.00)[2607:f8b0:4864:20::1136:from,209.85.128.178:received]; TO_MATCH_ENVRCPT_ALL(0.00)[]; RCVD_TLS_LAST(0.00)[]; PREVIOUSLY_DELIVERED(0.00)[freebsd-riscv@freebsd.org]; RCVD_COUNT_THREE(0.00)[3]; DKIM_TRACE(0.00)[cedro.info:+] X-Rspamd-Queue-Id: 4XMBw96V1fz4b4V X-Spamd-Bar: --- --0000000000007144360623d3ce26 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable :-) -- CeDeROM, SQ7MHZ, http://www.tomek.cedro.info ---------- Forwarded message --------- RISC-V International - RISC-V Synergy (Forums, Technical Talks and Webinars) View in browser Soft RISC-V Systems Workshop - Call for Participation and Proposals [image: RISC-V International] Please join us on Nov 7 and 8, between 8am-12pm PDT, to attend the First Annual Soft RISC-V Systems Workshop (SRvS). The workshop is completely online and FREE to attend by Zoom, but you must register in advance. We have arranged for keynote presentations from all 6 major soft RISC-V platforms: Achronix+Bluespec, AMD MicroBlazeV, Efinix+VexRiscV, Intel NIOS V, Lattice Semiconductor's RX, and Microsemi's Mi-V. Now that the open instruction set architecture of RISC-V has been adopted by all major FPGA vendors, users and vendors might begin to align their goals for CPUs, SoC systems design, and software tooling. Soft CPUs and soft SoC systems offer the most flexibility for customization, but they can also provide so much diversity that tooling becomes more difficult. Establishing common tooling, standards, interfaces, and policies helps to provide consistency needed by users for designing and supporting their soft RISC-V systems. The workshop will be a technically focused, inclusive celebration of the world of RISC-V FPGA Soft Processor Systems, and the great diversity of designs, designers, and applications. Whether you use FPGA RISC-V systems in industry, research, education, or as a hobby, whether closed or open source, whether CPU cores, SoCs, gadgets, software, or application, whether this is your tenth system or your first, we want to hear your story. Presentations may be traditional, or they may include a live or prerecorded demo. Please help us spread the word and join us as attendee or presenter. Website: https://sites.google.com/view/srvs-workshop FREE registration: https://community.riscv.org/e/m94ufu/ Propose a talk (deadline Oct 13): https://forms.gle/PUpkQkqZDcv6mfgC8 Upcoming Event Thursday, November 7 2024 First Annual Soft RISC-V Systems Workshop Virtual Event A technical workshop on the design of RISC-V processors and systems for FPGAs Get your ticket Stay engaged with the latest discussions: Megan Lehn has posted the discussion Can I attend the full conference? 2 days, 2 hours ago --0000000000007144360623d3ce26 Content-Type: text/html; charset="UTF-8" Content-Transfer-Encoding: quoted-printable
:-)

--
CeDeROM, SQ7MHZ, <= a href=3D"http://www.tomek.cedro.info">http://www.tomek.cedro.info
---------- Forwarded message ---------
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=20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20 =20
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=20 RISC-V International - RISC-V Synergy (Forums, Tech= nical Talks and Webinars) =20 View in browser
=20 =20 =20 =20 =20 =20 =20 =20
=20
Soft RISC-V Systems Worksho= p - Call for Participation and Proposals
=20 =20 3D"RISC-V =20 =20
=20 =20 =20
Please join us on Nov 7 and 8, between 8am-12pm PDT= , to attend the First Annual Soft RISC-V Systems Workshop (SRvS). The works= hop is completely online and FREE to attend by Zoom, but you must register = in advance.
We have arranged for keynote prese= ntations from all 6 major soft RISC-V platforms: Achronix+Bluespec, AMD Mic= roBlazeV, Efinix+VexRiscV, Intel NIOS V, Lattice Semiconductor's RX, an= d Microsemi's Mi-V. Now that the open instruction set architecture of R= ISC-V has been adopted by all major FPGA vendors, users and vendors might = begin to align their goals for CPUs, SoC systems design, and software tooli= ng. Soft CPUs and soft SoC systems offer the most flexibility for customiza= tion, but they can also provide so much diversity that tooling becomes more= difficult. Establishing common tooling, standards, interfaces, and policie= s helps to provide consistency needed by users for designing and supporting= their soft RISC-V systems.
The workshop will = be a technically focused, inclusive celebration of the world of RISC-V FPGA= Soft Processor Systems, and the great diversity of designs, designers, and= applications. Whether you use FPGA RISC-V systems in industry, research, e= ducation, or as a hobby, whether closed or open source, whether CPU cores, = SoCs, gadgets, software, or application, whether this is your tenth system = or your first, we want to hear your story. Presentations may be traditional= , or they may include a live or prerecorded demo.
=
Please help us spread the word and join us as attendee or presenter.
Website:
=
https://sites.google.com/view/srvs-workshop
FREE registration:
https://community.riscv.org/e/m94uf= u/
Propose a talk (deadline Oct 13)= :
=
https://forms.gle/PUpkQkqZDcv6mfgC8
=20 =20 =20 =20
Upcoming Event
=20 =20 =20 =20
=20 =20
=20 =20 =20 =20 =20
=20 3D"" =20 =20 =20
Thursday, November 7
2024 First Annual Soft RISC-V Systems W= orkshop
Virtual Event
=20 A technical workshop on the design of R= ISC-V processors and systems for FPGAs =20
Get your ticket
=20
=20 =20
Stay engaged with the latest discussions:
=20 =20 <= img src=3D"https://res.cloudinary.com/startup-grind/image/fetch/c_fill,dpr_= 2.0,f_auto,g_center,h_36,q_auto:good,w_36/https://res.cloudinary.com/startu= p-grind/image/upload/c_fill%2Cw_250%2Ch_250%2Cg_center/c_fill%2Cdpr_2.0%2Cf= _auto%2Cg_center%2Cq_auto:good/v1/gcs/platform-data-riscv/avatars/megan_leh= n.jpg" width=3D"36px" height=3D"36px" style=3D"border-radius:8px"> =20 =20 =20 Megan Lehn h= as posted the discussion Can I attend the full conference?
=20 =20 2=C2=A0days, 2=C2=A0hours ago
=20 =20 =20

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