Date: Sun, 02 Feb 1997 17:03:18 -0700 From: Steve Passe <smp@csn.net> To: Terry Lambert <terry@lambert.org> Cc: davem@jenolan.rutgers.edu, michaelh@cet.co.jp, netdev@roxanne.nuclecu.unam.mx, roque@di.fc.ul.pt, freebsd-smp@FreeBSD.org, smpdev@roxanne.nuclecu.unam.mx Subject: Re: SMP Message-ID: <199702030003.RAA11312@clem.systemsix.com> In-Reply-To: Your message of "Sun, 02 Feb 1997 16:25:26 MST." <199702022325.QAA09083@phaeton.artisoft.com>
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> > i missed something here, could you clarify exactly what "this case" > > means as reguards "seeing APIC_IO problems"? > > [ ... ] > > > > I have a theory about why this particular board is unhappy, but I need > > further tests run before I can verify anything. But I don't think it > > has anything to do with interaction of the APIC and cache coherency. > > OK... your theory is probably more likely correct than mine. > > What do you have to say about treating the cache line coherency? > Is it necessary, or is it automatic? I don't have a clue. I was under the belief that we have a MESI compliant board to deal with, but I could easily be wrong about that. I am the primary author of the FreeBSD APIC code and thus know the part pretty well. Its primary job is as a bus-oriented replacement for the 8259 ICUs. Among other features it provides IPI (InterProcessorInterrupts) facilities for communicating the need for TLB flushes, etc. between CPUs. Cache coherency is provided by the features of the P5/P6 chips and whatever MB glue their specifications require in an MP board. The Intel MP spec gives this only lip service. See the MP spec, ver 1.4, sections 3.3: External Cache SubSystem and appendix B.6: Other IPI Applications, for details. The spec can be found at: http://www.intel.com/design/pro/datashts/242016.htm Among the claims in the above mentioned spec: ------------------------------------ cut -------------------------------------- Maintaining cache coherency: When one processor accesses data cached in another processor's cache, it must not receive incorrect data. If it modifies data, all other processors that access that data also must not receive stale data. External caches must maintain coherency among themselves, and with the main memory, internal caches, and other bus master DMA devices. Cache flushing: The processor can generate special flush and write-back bus cycles that must be used by external caches in a manner that maintains cache coherency. The actual responses are implementation-specific and may vary from design to design. A program can initiate hardware cache flushing by executing a WBINVD instruction. This instruction is only guaranteed to flush the caches of the local processor. See Appendix B for system-wide flushing mechanisms. Given that cache coherency is maintained by hardware, there is no need for software to issue cache flush instructions under normal circumstances. ------------------------------------ cut -------------------------------------- --- For those of you new to the FreeBSD MP project, you can checkout: http://www.freebsd.org/~fsmp/SMP/SMP.html -- Steve Passe | powered by smp@csn.net | FreeBSD -----BEGIN PGP PUBLIC KEY BLOCK----- Version: 2.6.2 mQCNAzHe7tEAAAEEAM274wAEEdP+grIrV6UtBt54FB5ufifFRA5ujzflrvlF8aoE 04it5BsUPFi3jJLfvOQeydbegexspPXL6kUejYt2OeptHuroIVW5+y2M2naTwqtX WVGeBP6s2q/fPPAS+g+sNZCpVBTbuinKa/C4Q6HJ++M9AyzIq5EuvO0a8Rr9AAUR tBlTdGV2ZSBQYXNzZSA8c21wQGNzbi5uZXQ+ =ds99 -----END PGP PUBLIC KEY BLOCK-----
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