From owner-freebsd-current@FreeBSD.ORG Thu Sep 4 02:02:22 2008 Return-Path: Delivered-To: freebsd-current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 561FF106569E for ; Thu, 4 Sep 2008 02:02:22 +0000 (UTC) (envelope-from ticso@cicely7.cicely.de) Received: from raven.bwct.de (raven.bwct.de [85.159.14.73]) by mx1.freebsd.org (Postfix) with ESMTP id F0E988FC08 for ; Thu, 4 Sep 2008 02:02:21 +0000 (UTC) (envelope-from ticso@cicely7.cicely.de) Received: from cicely5.cicely.de ([10.1.1.7]) by raven.bwct.de (8.13.4/8.13.4) with ESMTP id m8422KDL018157 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=OK); Thu, 4 Sep 2008 04:02:20 +0200 (CEST) (envelope-from ticso@cicely7.cicely.de) Received: from cicely7.cicely.de (cicely7.cicely.de [10.1.1.9]) by cicely5.cicely.de (8.14.2/8.14.2) with ESMTP id m8422Fdw003106 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NO); Thu, 4 Sep 2008 04:02:16 +0200 (CEST) (envelope-from ticso@cicely7.cicely.de) Received: from cicely7.cicely.de (localhost [127.0.0.1]) by cicely7.cicely.de (8.14.2/8.14.2) with ESMTP id m8422F3Q015384; Thu, 4 Sep 2008 04:02:15 +0200 (CEST) (envelope-from ticso@cicely7.cicely.de) Received: (from ticso@localhost) by cicely7.cicely.de (8.14.2/8.14.2/Submit) id m8422Fw4015383; Thu, 4 Sep 2008 04:02:15 +0200 (CEST) (envelope-from ticso) Date: Thu, 4 Sep 2008 04:02:15 +0200 From: Bernd Walter To: David Malone Message-ID: <20080904020215.GB15328@cicely7.cicely.de> References: <20080903034943.GD11548@cicely7.cicely.de> <20080903204759.GA4898@walton.maths.tcd.ie> <20080903234642.GA14659@cicely7.cicely.de> <20080904015507.GA15328@cicely7.cicely.de> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20080904015507.GA15328@cicely7.cicely.de> X-Operating-System: FreeBSD cicely7.cicely.de 7.0-STABLE i386 User-Agent: Mutt/1.5.11 X-Spam-Status: No, score=-4.3 required=5.0 tests=ALL_TRUSTED=-1.8, AWL=0.069, BAYES_00=-2.599 autolearn=ham version=3.2.5 X-Spam-Checker-Version: SpamAssassin 3.2.5 (2008-06-10) on spamd.cicely.de Cc: Bernd Walter , freebsd-current@freebsd.org, ticso@cicely.de Subject: Re: MTRR fixup? X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list Reply-To: ticso@cicely.de List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 04 Sep 2008 02:02:22 -0000 On Thu, Sep 04, 2008 at 03:55:07AM +0200, Bernd Walter wrote: > On Thu, Sep 04, 2008 at 01:46:42AM +0200, Bernd Walter wrote: > > On Wed, Sep 03, 2008 at 09:47:59PM +0100, David Malone wrote: > > > On Wed, Sep 03, 2008 at 05:49:44AM +0200, Bernd Walter wrote: > > > > Some boards (including my Intel DG33BU) seem to have problems setting > > > > up the mtrr to cache all RAM. > > > > My system runs fast with 2G and ist about 6 times slower in buildworld > > > > with 6G RAM. > > > > I will try a BIOS update once Intels tells me why their update ISO > > > > just turn the system off instead of updating the BIOS - sigh. > > > > But it seems that Linux is doing some kind of fixup for MTRR: > > > > http://lkml.org/lkml/2008/1/18/170 > > > > Can we do something similar? > > > > > > You may be able to fix this by just using the memcontrol command - > > > it already lets you program the MTRRs. > > > > Oh damn - a new fancy tool to play with ;-) > > > > Interesting - the values look good: > > [...] > > 0x0/0x80000000 ticso write-back active > > 0x80000000/0x40000000 ticso write-back active > > 0xc0000000/0x10000000 ticso write-back active > > 0xcf800000/0x800000 BIOS uncacheable set-by-firmware active > > 0xcf400000/0x400000 BIOS uncacheable set-by-firmware active > > 0x100000000/0x80000000 ticso write-back active > > 0x180000000/0x20000000 ticso write-back active > > 0x0/0x1000000000 - uncacheable > > Ok - there it is - something is missing: > ram0 > I/O memory addresses: > 0x0-0x9c3ff > 0x100000-0xcf212fff > 0xcf215000-0xcf2fafff > 0xcf3e5000-0xcf3e8fff > 0xcf3f2000-0xcf3f2fff > 0xcf3ff000-0xcf3fffff > 0x100000000-0x1abffffff > > ram goes up to 0x1abffffff mtrr just goes up to 0x1a0000000 - 1, so the > last 192MB are uncached. > But memcontrol complains when trying to add the range: > [55]cicely14# memcontrol set -b 0x1a0000000 -l 0xc000000 -o ticso write-back > memcontrol: can't set range: Invalid argument Ok - I more or less got it. I have to set 2^n ranges. The first one goes: [56]cicely14# memcontrol set -b 0x1a0000000 -l 0x8000000 -o ticso write-back The second not: [57]cicely14# memcontrol set -b 0x1a8000000 -l 0x4000000 -o ticso write-back memcontrol: can't set range: No space left on device Exit 1 But this is exactly my problem, because if I only set the second one the board instantly speeds up. Something important of the system must be in the last 64MB. Nevertheless I can't use memcontrol to setup everything as cacheable. I could set hw.phymem to get the kernel below the last 64MB or maybe even the last 192MB. If someone has an idea on how to set both ranges... But anyway: Thank you all - this was very usefull, since I can now get almost all memory without massive performance penalty. -- B.Walter http://www.bwct.de Modbus/TCP Ethernet I/O Baugruppen, ARM basierte FreeBSD Rechner uvm.