From owner-svn-src-head@freebsd.org Tue Jun 13 18:50:09 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 4E41DBFBF49; Tue, 13 Jun 2017 18:50:09 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 2AA3A2D48; Tue, 13 Jun 2017 18:50:09 +0000 (UTC) (envelope-from zbb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v5DIo87C030888; Tue, 13 Jun 2017 18:50:08 GMT (envelope-from zbb@FreeBSD.org) Received: (from zbb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v5DIo8qi030887; Tue, 13 Jun 2017 18:50:08 GMT (envelope-from zbb@FreeBSD.org) Message-Id: <201706131850.v5DIo8qi030887@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: zbb set sender to zbb@FreeBSD.org using -f From: Zbigniew Bodek Date: Tue, 13 Jun 2017 18:50:08 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r319910 - head/sys/arm/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jun 2017 18:50:09 -0000 Author: zbb Date: Tue Jun 13 18:50:08 2017 New Revision: 319910 URL: https://svnweb.freebsd.org/changeset/base/319910 Log: Add detection of CPU class for ARMv6/v7 Submitted by: Michal Mazur Obtained from: Semihalf Sponsored by: Stormshield Reviewed by: andrew Differential revision: https://reviews.freebsd.org/D10909 Modified: head/sys/arm/arm/identcpu-v6.c Modified: head/sys/arm/arm/identcpu-v6.c ============================================================================== --- head/sys/arm/arm/identcpu-v6.c Tue Jun 13 18:48:51 2017 (r319909) +++ head/sys/arm/arm/identcpu-v6.c Tue Jun 13 18:50:08 2017 (r319910) @@ -60,29 +60,47 @@ static char hw_buf[81]; static int hw_buf_idx; static bool hw_buf_newline; +enum cpu_class cpu_class = CPU_CLASS_NONE; + static struct { int implementer; int part_number; char *impl_name; char *core_name; + enum cpu_class cpu_class; } cpu_names[] = { - {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72"}, - {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73"}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_ARM1176, "ARM", "ARM1176", + CPU_CLASS_ARM11J}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A5 , "ARM", "Cortex-A5", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A7 , "ARM", "Cortex-A7", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A8 , "ARM", "Cortex-A8", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A9 , "ARM", "Cortex-A9", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A12, "ARM", "Cortex-A12", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A15, "ARM", "Cortex-A15", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A17, "ARM", "Cortex-A17", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A53, "ARM", "Cortex-A53", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A57, "ARM", "Cortex-A57", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A72, "ARM", "Cortex-A72", + CPU_CLASS_CORTEXA}, + {CPU_IMPLEMENTER_ARM, CPU_ARCH_CORTEX_A73, "ARM", "Cortex-A73", + CPU_CLASS_CORTEXA}, - {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7"}, - {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7"}, + {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_581, "Marwell", "PJ4 v7", + CPU_CLASS_MARVELL}, + {CPU_IMPLEMENTER_MRVL, CPU_ARCH_SHEEVA_584, "Marwell", "PJ4MP v7", + CPU_CLASS_MARVELL}, - {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300"}, + {CPU_IMPLEMENTER_QCOM, CPU_ARCH_KRAIT_300, "Qualcomm", "Krait 300", + CPU_CLASS_KRAIT}, }; @@ -266,6 +284,7 @@ identify_arm_cpu(void) for(i = 0; i < nitems(cpu_names); i++) { if (cpu_names[i].implementer == cpuinfo.implementer && cpu_names[i].part_number == cpuinfo.part_number) { + cpu_class = cpu_names[i].cpu_class; printf("CPU: %s %s r%dp%d (ECO: 0x%08X)\n", cpu_names[i].impl_name, cpu_names[i].core_name, cpuinfo.revision, cpuinfo.patch,