Date: Tue, 13 Jul 2004 09:17:18 +0200 From: des@des.no (=?iso-8859-1?q?Dag-Erling_Sm=F8rgrav?=) To: Steven Smith <sos22@cantab.net> Cc: sos22@srcf.ucam.org Subject: Re: Article on Sun's DTrace Message-ID: <xzp3c3wgyv5.fsf@dwp.des.no> In-Reply-To: <20040712180933.GA1093@archibold.chu.cam.ac.uk> (Steven Smith's message of "Mon, 12 Jul 2004 19:09:33 %2B0100") References: <1089501790.00086820.1089489001@10.7.7.3> <20040712115134.D6C3F14F@pm514-9.comsys.ntu-kpi.kiev.ua> <20040712180933.GA1093@archibold.chu.cam.ac.uk>
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Steven Smith <sos22@cantab.net> writes: > I don't know enough about Sparcs to even speculate how it's done > there. The UltraSparc is a RISC processor, which amongst other things implies constant instruction size. Memory barriers take care of any cache coherence issues that may arise. DES --=20 Dag-Erling Sm=F8rgrav - des@des.no
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