From owner-svn-src-head@freebsd.org Mon Jul 9 16:42:48 2018 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id E530E1038DC1 for ; Mon, 9 Jul 2018 16:42:47 +0000 (UTC) (envelope-from wma@semihalf.com) Received: from mail-it0-x22f.google.com (mail-it0-x22f.google.com [IPv6:2607:f8b0:4001:c0b::22f]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (Client CN "smtp.gmail.com", Issuer "Google Internet Authority G2" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 77A2D78666 for ; Mon, 9 Jul 2018 16:42:47 +0000 (UTC) (envelope-from wma@semihalf.com) Received: by mail-it0-x22f.google.com with SMTP id p4-v6so26293859itf.2 for ; Mon, 09 Jul 2018 09:42:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=semihalf-com.20150623.gappssmtp.com; s=20150623; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc; bh=F0EI7XeJLYxcCmk9urcO76/dY23VbaYiwcGxyMbhqpg=; b=AvA2u7KHbsBg4RyLGuGDwIB8CSR9G3hOhCJShYfly1ecjaMsqV8wqSiIXAyg+tPqym SaoeDxXdw9vybGjnOUWl7fd1NIi3uXVkeRtrEUlA0qL843t2IwX7Pz5JOQHjQW3rGKuC jGZN1wzwsS18u012JNUkaxZ71FlAOCtK1Z9FtQKRNwQo79thzHRvQEP6qzHayuvJ7KQ7 5lNLb3J5HJJtaMuLdtKzxszK5VOJuS2kb8JjlDVV/gRQd3m/glRJKdldnB8QloF1WE59 zjHLtpslmO0i6+YhmUsBgvQmTpKlhCRcSJlX0MVbZ0GeXMb0Q9jLFPQy938TwIKtVyIE g/RQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:in-reply-to:references:from:date :message-id:subject:to:cc; bh=F0EI7XeJLYxcCmk9urcO76/dY23VbaYiwcGxyMbhqpg=; b=FC1Snwb3Dmnoy34L1Z4gnm/2oBUdtrwsB01lmxjgXhIRk/UORawRxam6e5MqECANvk XLFOlbUnXTJ0H+LY0O4HA0WrjBYVT8PmMbAH0lTAJ/6xNvLrMEsGe0be/u5D6eqeN2SX TV/zBROcIjKGEk9Nvo0CCMqEXPbfxFoCmBjJFfkDnBwj+0Al9apITJSBdjg1aoyfWS/U sUU0nkUSjVQ/T8BvNSEAjXs42sqwCDx1Rqewlk11CpRS1fPIqTqrKDfTn7R/C9/J0DFR 1Fwc3sGUoowmVLPfMdriqZ0654v0hAtNKF5seP/kRnZleBVl9pCBjQ0GCygPCeZs4ZM/ c3wQ== X-Gm-Message-State: APt69E0xtwK2TmiSaS3RgUJw9aZTav0asy6qHuzXC9Q0qHOJeEFBkUiF XQ8hh3x0Qv3yG3KbvXQV1G0OWfl5UrtCQ7vDrkQc2g== X-Google-Smtp-Source: AAOMgpd/l5kvuKJNwSWioZH7NFb2gWhvy44vyVzPGhvCzQXu+LLnw5rGIGrtv2swsEk7ciMFTuFrog1WjcSxVf2GlV8= X-Received: by 2002:a24:9bc2:: with SMTP id o185-v6mr16714365itd.77.1531154566742; Mon, 09 Jul 2018 09:42:46 -0700 (PDT) MIME-Version: 1.0 Received: by 2002:a6b:91c6:0:0:0:0:0 with HTTP; Mon, 9 Jul 2018 09:42:26 -0700 (PDT) In-Reply-To: References: <201807090900.w6990GCZ081981@repo.freebsd.org> From: Wojciech Macek Date: Mon, 9 Jul 2018 18:42:26 +0200 Message-ID: Subject: Re: svn commit: r336130 - head/sys/dev/pci To: Nathan Whitehorn Cc: Andrew Turner , Wojciech Macek , src-committers , svn-src-all@freebsd.org, svn-src-head@freebsd.org, Patryk Duda Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.27 X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.27 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 09 Jul 2018 16:42:48 -0000 We will fix it, sorry for troubles. @wma 2018-07-09 18:10 GMT+02:00 Nathan Whitehorn : > Maybe this file should be renamed and/or split anyway? It's not actually > very generic and is used only on (some) ARM systems. > -Nathan > > > On 07/09/18 09:00, Andrew Turner wrote: > >> This breaks at least armv7. Please either fix, or revert this. >> >> I have some comments below I was planning on adding to the review, but >> you committed before I had the time to do so. >> >> On 9 Jul 2018, at 10:00, Wojciech Macek wrote: >>> >>> Author: wma >>> Date: Mon Jul 9 09:00:16 2018 >>> New Revision: 336130 >>> URL: https://svnweb.freebsd.org/changeset/base/336130 >>> >>> Log: >>> ARM64: Add quirk mechanism to pci_host_generic_acpi >>> >>> Add few quirks which are necessary to use AHCI on ThX2 >>> >>> Submitted by: Patryk Duda >>> Obtained from: Semihalf >>> Sponsored by: Cavium >>> Differential revision: https://reviews.freebsd.org/D15929 >>> >>> Modified: >>> head/sys/dev/pci/pci_host_generic.c >>> >>> Modified: head/sys/dev/pci/pci_host_generic.c >>> ============================================================ >>> ================== >>> --- head/sys/dev/pci/pci_host_generic.c Mon Jul 9 08:55:07 2018 >>> (r336129) >>> +++ head/sys/dev/pci/pci_host_generic.c Mon Jul 9 09:00:16 2018 >>> (r336130) >>> @@ -69,6 +69,25 @@ __FBSDID("$FreeBSD$"); >>> (((func) & PCIE_FUNC_MASK) << PCIE_FUNC_SHIFT) | \ >>> ((reg) & PCIE_REG_MASK)) >>> >>> +typedef void (*pci_host_generic_quirk_function)(device_t); >>> + >>> +struct pci_host_generic_quirk_entry { >>> + int impl; >>> + int part; >>> + int var; >>> + int rev; >>> + pci_host_generic_quirk_function func; >>> +}; >>> + >>> +struct pci_host_generic_block_entry { >>> + int impl; >>> + int part; >>> + int var; >>> + int rev; >>> + int bus; >>> + int slot; >>> +}; >>> + >>> /* Forward prototypes */ >>> >>> static uint32_t generic_pcie_read_config(device_t dev, u_int bus, u_int >>> slot, >>> @@ -80,7 +99,22 @@ static int generic_pcie_read_ivar(device_t dev, >>> device >>> uintptr_t *result); >>> static int generic_pcie_write_ivar(device_t dev, device_t child, int >>> index, >>> uintptr_t value); >>> +static void pci_host_generic_apply_quirks(device_t); >>> +static void thunderx2_ahci_bar_quirk(device_t); >>> >>> +struct pci_host_generic_quirk_entry pci_host_generic_quirks[] = >>> +{ >>> + {CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, >>> thunderx2_ahci_bar_quirk}, >>> + {0, 0, 0, 0, NULL} >>> >> This breaks non-arm64, please fix. >> >> +}; >>> + >>> +struct pci_host_generic_block_entry pci_host_generic_blocked[] = >>> +{ >>> + /* ThunderX2 AHCI on second socket */ >>> + {CPU_IMPL_CAVIUM, CPU_PART_THUNDERX2, 0, 0, 0x80, 0x10}, >>> + {0, 0, 0, 0, 0, 0} >>> >> And this. >> >> +}; >>> + >>> int >>> pci_host_generic_core_attach(device_t dev) >>> { >>> @@ -134,9 +168,30 @@ pci_host_generic_core_attach(device_t dev) >>> return (error); >>> } >>> >>> + pci_host_generic_apply_quirks(dev); >>> + >>> return (0); >>> } >>> >>> +static void >>> +pci_host_generic_apply_quirks(device_t dev) >>> +{ >>> + struct pci_host_generic_quirk_entry *quirk; >>> + >>> + quirk = pci_host_generic_quirks; >>> + while (1) { >>> + if (quirk->impl == 0) >>> + break; >>> + >>> + if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, >>> + quirk->impl, quirk->part, quirk->var, quirk->rev) && >>> + quirk->func != NULL) >>> >> This is arm64 specific. >> >> + quirk->func(dev); >>> + >>> + quirk++; >>> + } >>> +} >>> + >>> static uint32_t >>> generic_pcie_read_config(device_t dev, u_int bus, u_int slot, >>> u_int func, u_int reg, int bytes) >>> @@ -146,11 +201,25 @@ generic_pcie_read_config(device_t dev, u_int bus, >>> u_in >>> bus_space_tag_t t; >>> uint64_t offset; >>> uint32_t data; >>> + struct pci_host_generic_block_entry *block; >>> >>> if ((bus > PCI_BUSMAX) || (slot > PCI_SLOTMAX) || >>> (func > PCI_FUNCMAX) || (reg > PCIE_REGMAX)) >>> return (~0U); >>> >>> + block = pci_host_generic_blocked; >>> + while (1) { >>> + if (block->impl == 0) >>> + break; >>> + >>> + if (CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK, >>> + block->impl, block->part, block->var, block->rev) && >>> + block->bus == bus && block->slot == slot) >>> >> This is also arm64 specific. >> >> + return (~0); >>> + >>> + block++; >>> + } >>> + >>> sc = device_get_softc(dev); >>> >>> offset = PCIE_ADDR_OFFSET(bus, slot, func, reg); >>> @@ -392,3 +461,20 @@ static device_method_t generic_pcie_methods[] = { >>> >>> DEFINE_CLASS_0(pcib, generic_pcie_core_driver, >>> generic_pcie_methods, sizeof(struct generic_pcie_core_softc)); >>> + >>> +static void thunderx2_ahci_bar_quirk(device_t dev) >>> >> This should be dependent on arm64 and an appropriate SOC_ check. >> >> +{ >>> + >>> + /* >>> + * XXX: >>> + * On ThunderX2, AHCI BAR2 address is wrong. It needs to >>> precisely >>> + * match the one described in datasheet. Fixup it >>> unconditionally. >>> + */ >>> + if (device_get_unit(dev) == 0) { >>> + device_printf(dev, "running AHCI BAR fixup\n"); >>> + PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x18, 0x01440000, 4); >>> + PCIB_WRITE_CONFIG(dev, 0, 16, 0, 0x1c, 0x40, 4); >>> + PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x18, 0x01450000, 4); >>> + PCIB_WRITE_CONFIG(dev, 0, 16, 1, 0x1c, 0x40, 4); >>> + } >>> +} >>> >> Andrew >> >> >> >> >