From owner-svn-src-all@freebsd.org Mon Apr 18 06:15:59 2016 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 8BF7DB114B3; Mon, 18 Apr 2016 06:15:59 +0000 (UTC) (envelope-from sgalabov@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 42A8A117A; Mon, 18 Apr 2016 06:15:59 +0000 (UTC) (envelope-from sgalabov@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id u3I6FwAR037070; Mon, 18 Apr 2016 06:15:58 GMT (envelope-from sgalabov@FreeBSD.org) Received: (from sgalabov@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id u3I6Fw19037068; Mon, 18 Apr 2016 06:15:58 GMT (envelope-from sgalabov@FreeBSD.org) Message-Id: <201604180615.u3I6Fw19037068@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: sgalabov set sender to sgalabov@FreeBSD.org using -f From: Stanislav Galabov Date: Mon, 18 Apr 2016 06:15:58 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r298185 - head/sys/mips/mediatek X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Apr 2016 06:15:59 -0000 Author: sgalabov Date: Mon Apr 18 06:15:58 2016 New Revision: 298185 URL: https://svnweb.freebsd.org/changeset/base/298185 Log: Allow RT3350 CPU clock to be detected as part of RT3050/RT3052 detection OpenWRT's dts files treat RT3050/RT3052/RT3350 within the same SoC dtsi file, so we need to distinguish between the three dynamically, mainly because the bit we use to determine the clock speed on RT3050/RT3052 can actually be floating on RT3350 and RT3350 is always at 320MHz. Approved by: adrian (mentor) Sponsored by: Smartcom - Bulgaria AD Differential Revision: https://reviews.freebsd.org/D5983 Modified: head/sys/mips/mediatek/mtk_soc.c head/sys/mips/mediatek/mtk_sysctl.h Modified: head/sys/mips/mediatek/mtk_soc.c ============================================================================== --- head/sys/mips/mediatek/mtk_soc.c Mon Apr 18 06:12:00 2016 (r298184) +++ head/sys/mips/mediatek/mtk_soc.c Mon Apr 18 06:15:58 2016 (r298185) @@ -76,13 +76,17 @@ static const struct ofw_compat_data comp static uint32_t mtk_detect_cpuclk_rt305x(bus_space_tag_t bst, bus_space_handle_t bsh) { - uint32_t clk; + uint32_t val; + + val = bus_space_read_4(bst, bsh, SYSCTL_CHIPID0_3); + if (val == RT3350_CHIPID0_3) + return (MTK_CPU_CLK_320MHZ); - clk = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); - clk >>= RT305X_CPU_CLKSEL_OFF; - clk &= RT305X_CPU_CLKSEL_MSK; + val = bus_space_read_4(bst, bsh, SYSCTL_SYSCFG); + val >>= RT305X_CPU_CLKSEL_OFF; + val &= RT305X_CPU_CLKSEL_MSK; - return ((clk == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ); + return ((val == 0) ? MTK_CPU_CLK_320MHZ : MTK_CPU_CLK_384MHZ); } static uint32_t @@ -265,10 +269,8 @@ mtk_soc_try_early_detect(void) switch (mtk_soc_socid) { case MTK_SOC_RT3050: /* fallthrough */ case MTK_SOC_RT3052: - mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh); - break; case MTK_SOC_RT3350: - mtk_soc_cpuclk = MTK_CPU_CLK_320MHZ; + mtk_soc_cpuclk = mtk_detect_cpuclk_rt305x(bst, bsh); break; case MTK_SOC_RT3352: mtk_soc_cpuclk = mtk_detect_cpuclk_rt3352(bst, bsh); Modified: head/sys/mips/mediatek/mtk_sysctl.h ============================================================================== --- head/sys/mips/mediatek/mtk_sysctl.h Mon Apr 18 06:12:00 2016 (r298184) +++ head/sys/mips/mediatek/mtk_sysctl.h Mon Apr 18 06:15:58 2016 (r298185) @@ -52,6 +52,8 @@ #define SYSCFG1_USB_HOST_MODE (1<<10) +#define RT3350_CHIPID0_3 0x33335452 + extern uint32_t mtk_sysctl_get(uint32_t); extern void mtk_sysctl_set(uint32_t, uint32_t); extern void mtk_sysctl_clr_set(uint32_t, uint32_t, uint32_t);