From owner-freebsd-hardware Fri Jan 9 05:35:03 1998 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.7/8.8.7) id FAA19902 for hardware-outgoing; Fri, 9 Jan 1998 05:35:03 -0800 (PST) (envelope-from owner-freebsd-hardware) Received: from verdi.nethelp.no (verdi.nethelp.no [195.1.171.130]) by hub.freebsd.org (8.8.7/8.8.7) with SMTP id FAA19878 for ; Fri, 9 Jan 1998 05:34:51 -0800 (PST) (envelope-from sthaug@nethelp.no) From: sthaug@nethelp.no Received: (qmail 27005 invoked by uid 1001); 9 Jan 1998 13:34:44 +0000 (GMT) To: grog@lemis.com Cc: hardware@freebsd.org Subject: Re: LS-120, Riva 128, ASUS motherboard In-Reply-To: Your message of "Fri, 9 Jan 1998 19:40:06 +1030" References: <19980109194006.42229@lemis.com> X-Mailer: Mew version 1.05+ on Emacs 19.28.2 Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Date: Fri, 09 Jan 1998 14:34:44 +0100 Message-ID: <27003.884352884@verdi.nethelp.no> Sender: owner-freebsd-hardware@freebsd.org X-Loop: FreeBSD.org Precedence: bulk > Ahh. http://www.intel.com/design/pcisets/datashts/290559.htm. > Extract: > > The Intel 430TX PCIset (430TX) consists of the 82439TX System > Controller (MTXC) and the 82371AB PCI ISA IDE Xcelerator > (PIIX4). [...] The MTXC integrates the cache and main memory DRAM > control functions and provides bus control to transfers between the > CPU, cache, main memory, and the PCI Bus. The second level (L2) > cache controller supports a writeback cache policy for cache sizes > of 256 Kbytes and 512 Kbytes. > > I'm downloading the document, and will print it out, but this > certainly doesn't sound like Tom's Hardware Guide. I have something called "Intel 430TX PCIset: 82439TX System Controller". It states very clearly on the first page: "64 MB DRAM Cacheability"/ Steinar Haug, Nethelp consulting, sthaug@nethelp.no