From owner-svn-src-all@FreeBSD.ORG Wed Oct 22 08:23:43 2008 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id A1FEE1065675; Wed, 22 Oct 2008 08:23:43 +0000 (UTC) (envelope-from sos@freebsd.org) Received: from deepcore.dk (adsl.deepcore.dk [87.63.29.106]) by mx1.freebsd.org (Postfix) with ESMTP id 204D58FC19; Wed, 22 Oct 2008 08:23:42 +0000 (UTC) (envelope-from sos@freebsd.org) Received: from [172.18.2.117] (axiell-gw1.novi.dk [77.243.61.137]) by deepcore.dk (8.14.3/8.14.2) with ESMTP id m9M7lMIw099226; Wed, 22 Oct 2008 09:47:22 +0200 (CEST) (envelope-from sos@freebsd.org) Message-Id: <19AE8B2B-1C78-49EB-96D4-029FBFB9552E@freebsd.org> From: =?ISO-8859-1?Q?S=F8ren_Schmidt?= To: John Baldwin In-Reply-To: <200810171603.m9HG3buK092293@svn.freebsd.org> Content-Type: text/plain; charset=ISO-8859-1; format=flowed; delsp=yes Content-Transfer-Encoding: quoted-printable Mime-Version: 1.0 (Apple Message framework v929.2) Date: Wed, 22 Oct 2008 09:47:21 +0200 References: <200810171603.m9HG3buK092293@svn.freebsd.org> X-Mailer: Apple Mail (2.929.2) X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.0 (deepcore.dk [87.63.29.106]); Wed, 22 Oct 2008 09:47:22 +0200 (CEST) Cc: svn-src-head@freebsd.org, svn-src-all@freebsd.org, src-committers@freebsd.org Subject: Re: svn commit: r183981 - head/sys/dev/ata/chipsets X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 22 Oct 2008 08:23:43 -0000 Well, it has been busy around here.. Anyhow, I think this is an overly pessimistic change, I've not seen =20 nor heard about problems with the 63K transfer size on anything but =20 the HT1000 based machines. It seems that all serverworks chips are =20 bugridden in some way or another, just avoid :) On the MIO change, the original docs I got from serverworks states =20 that PCI id to not support MIO mode and be for compat/legacy setups, =20 so this might produce some hickups if thats true. However their docs are often as flawed as their silicon so, guess this =20= is up to the board/BIOS producer to decide. -S=F8ren On 17Oct, 2008, at 18:03 , John Baldwin wrote: > Author: jhb > Date: Fri Oct 17 16:03:37 2008 > New Revision: 183981 > URL: http://svn.freebsd.org/changeset/base/183981 > > Log: > - For chipsets that can't do 64k transfers, fall back to 32k =20 > transfers > (still a power of 2) rather than 63k transfers. Even with 63k =20 > transfers > some machines (such as Dell SC1435's) were experiencing chronic =20 > data > corruption. > - Use the MIO method to talk to the Serverworks HT1000_S1 SATA =20 > controller > like all the other SATA controllers rather than the compat PATA > method. This lets the controller see all 4 SATA ports and also > matches the behavior of the Linux driver. > > Silence from: sos > MFC after: 3 days > > Modified: > head/sys/dev/ata/chipsets/ata-cyrix.c > head/sys/dev/ata/chipsets/ata-marvell.c > head/sys/dev/ata/chipsets/ata-national.c > head/sys/dev/ata/chipsets/ata-serverworks.c > > Modified: head/sys/dev/ata/chipsets/ata-cyrix.c > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- head/sys/dev/ata/chipsets/ata-cyrix.c Fri Oct 17 15:11:12 2008 = =20 > (r183980) > +++ head/sys/dev/ata/chipsets/ata-cyrix.c Fri Oct 17 16:03:37 2008 = =20 > (r183981) > @@ -109,7 +109,7 @@ ata_cyrix_setmode(device_t dev, int mode > /* dont try to set the mode if we dont have the resource */ > if (ctlr->r_res1) { > ch->dma.alignment =3D 16; > - ch->dma.max_iosize =3D 126 * DEV_BSIZE; > + ch->dma.max_iosize =3D 64 * DEV_BSIZE; > > if (mode >=3D ATA_UDMA0) { > ATA_OUTL(ch->r_io[ATA_BMCMD_PORT].res, > > Modified: head/sys/dev/ata/chipsets/ata-marvell.c > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- head/sys/dev/ata/chipsets/ata-marvell.c Fri Oct 17 15:11:12 2008 = =20 > (r183980) > +++ head/sys/dev/ata/chipsets/ata-marvell.c Fri Oct 17 16:03:37 2008 = =20 > (r183981) > @@ -536,7 +536,7 @@ ata_marvell_edma_dmainit(device_t dev) > ch->dma.max_address =3D BUS_SPACE_MAXADDR; > > /* chip does not reliably do 64K DMA transfers */ > - ch->dma.max_iosize =3D 126 * DEV_BSIZE; > + ch->dma.max_iosize =3D 64 * DEV_BSIZE; > } > > ATA_DECLARE_DRIVER(ata_marvell); > > Modified: head/sys/dev/ata/chipsets/ata-national.c > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- head/sys/dev/ata/chipsets/ata-national.c Fri Oct 17 15:11:12 =20 > 2008 (r183980) > +++ head/sys/dev/ata/chipsets/ata-national.c Fri Oct 17 16:03:37 =20 > 2008 (r183981) > @@ -101,7 +101,7 @@ ata_national_setmode(device_t dev, int m > int error; > > ch->dma.alignment =3D 16; > - ch->dma.max_iosize =3D 126 * DEV_BSIZE; > + ch->dma.max_iosize =3D 64 * DEV_BSIZE; > > mode =3D ata_limit_mode(dev, mode, ATA_UDMA2); > > > Modified: head/sys/dev/ata/chipsets/ata-serverworks.c > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=20 > =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D > --- head/sys/dev/ata/chipsets/ata-serverworks.c Fri Oct 17 = 15:11:12 =20 > 2008 (r183980) > +++ head/sys/dev/ata/chipsets/ata-serverworks.c Fri Oct 17 = 16:03:37 =20 > 2008 (r183981) > @@ -79,7 +79,7 @@ ata_serverworks_probe(device_t dev) > { ATA_CSB6, 0x00, SWKS_100, 0, ATA_UDMA5, "CSB6" }, > { ATA_CSB6_1, 0x00, SWKS_66, 0, ATA_UDMA4, "CSB6" }, > { ATA_HT1000, 0x00, SWKS_100, 0, ATA_UDMA5, "HT1000" }, > - { ATA_HT1000_S1, 0x00, SWKS_100, 4, ATA_SA150, "HT1000" }, > + { ATA_HT1000_S1, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, > { ATA_HT1000_S2, 0x00, SWKS_MIO, 4, ATA_SA150, "HT1000" }, > { ATA_K2, 0x00, SWKS_MIO, 4, ATA_SA150, "K2" }, > { ATA_FRODO4, 0x00, SWKS_MIO, 4, ATA_SA150, "Frodo4" }, > @@ -184,7 +184,7 @@ ata_serverworks_allocate(device_t dev) > ch->hw.tf_write =3D ata_serverworks_tf_write; > > /* chip does not reliably do 64K DMA transfers */ > - ch->dma.max_iosize =3D 126 * DEV_BSIZE; > + ch->dma.max_iosize =3D 64 * DEV_BSIZE; > > return 0; > } > -S=F8ren